luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Modifications to give error messages rather than assertions

This commit is contained in:
Bill Lye 2022-12-30 10:36:38 -08:00
parent 0958621ad1
commit ee0c6bb5e4
2 changed files with 19 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
elab_expr.cc
View File

@ -6226,7 +6226,14 @@ NetExpr* PEIdent::elaborate_expr_net_bit_(Design*des, NetScope*scope,
unsigned long lwid; unsigned long lwid;
long idx; long idx;
rc = net->sig()->sb_to_slice(prefix_indices, msv, idx, lwid); rc = net->sig()->sb_to_slice(prefix_indices, msv, idx, lwid);
ivl_assert(*this, rc);
if(!rc) {
cerr << get_fileline() << ": error: Index " << net->sig()->name()
<< "[" << msv << "] is out of range."
<< endl;
des->errors += 1;
return 0;
}
// Make an expression out of the index // Make an expression out of the index
NetEConst*idx_c = new NetEConst(verinum(idx)); NetEConst*idx_c = new NetEConst(verinum(idx));

14
elab_net.cc
View File

@ -464,9 +464,17 @@ bool PEIdent::eval_part_select_(Design*des, NetScope*scope, NetNet*sig,
unsigned long tmp_lwid; unsigned long tmp_lwid;
bool rcl = sig->sb_to_slice(prefix_indices, msb, bool rcl = sig->sb_to_slice(prefix_indices, msb,
tmp_loff, tmp_lwid); tmp_loff, tmp_lwid);
ivl_assert(*this, rcl); if(rcl) {
midx = tmp_loff + tmp_lwid - 1; midx = tmp_loff + tmp_lwid - 1;
lidx = tmp_loff; lidx = tmp_loff;
} else {
cerr << get_fileline() << ": error: Index " << sig->name()
<< "[" << msb << "] is out of range."
<< endl;
des->errors += 1;
midx = 0;
lidx = 0;
}
} else { } else {
midx = sig->sb_to_idx(prefix_indices, msb); midx = sig->sb_to_idx(prefix_indices, msb);
if (midx >= (long)sig->vector_width()) { if (midx >= (long)sig->vector_width()) {