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Part selects are done in the compiler, not here.

This commit is contained in:
steve 2005-01-24 05:08:02 +00:00
parent 14f557e6f4
commit edeb9d8eca
2 changed files with 8 additions and 9 deletions
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9
tgt-vvp/eval_expr.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: eval_expr.c,v 1.111 2004/12/11 02:31:28 steve Exp $" #ident "$Id: eval_expr.c,v 1.112 2005/01/24 05:08:02 steve Exp $"
#endif #endif
# include "vvp_priv.h" # include "vvp_priv.h"
@ -1457,16 +1457,12 @@ static struct vector_info draw_string_expr(ivl_expr_t exp, unsigned wid)
static void draw_signal_dest(ivl_expr_t exp, struct vector_info res) static void draw_signal_dest(ivl_expr_t exp, struct vector_info res)
{ {
unsigned idx; unsigned idx;
unsigned lsi = ivl_expr_lsi(exp);
unsigned swid = ivl_expr_width(exp); unsigned swid = ivl_expr_width(exp);
ivl_signal_t sig = ivl_expr_signal(exp); ivl_signal_t sig = ivl_expr_signal(exp);
if (swid > res.wid) if (swid > res.wid)
swid = res.wid; swid = res.wid;
/* XXXX I forget how to do part selects here. */
assert(lsi == 0);
/* If this is a REG (a variable) then I can do a vector read. */ /* If this is a REG (a variable) then I can do a vector read. */
fprintf(vvp_out, " %%load/v %u, V_%s, %u;\n", fprintf(vvp_out, " %%load/v %u, V_%s, %u;\n",
res.base, vvp_signal_label(sig), swid); res.base, vvp_signal_label(sig), swid);
@ -2129,6 +2125,9 @@ struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
/* /*
* $Log: eval_expr.c,v $ * $Log: eval_expr.c,v $
* Revision 1.112 2005/01/24 05:08:02 steve
* Part selects are done in the compiler, not here.
*
* Revision 1.111 2004/12/11 02:31:28 steve * Revision 1.111 2004/12/11 02:31:28 steve
* Rework of internals to carry vectors through nexus instead * Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes * of single bits. Make the ivl, tgt-vvp and vvp initial changes

8
tgt-vvp/vector.c
View File

@ -16,7 +16,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: vector.c,v 1.4 2003/07/03 17:44:10 steve Exp $" #ident "$Id: vector.c,v 1.5 2005/01/24 05:08:02 steve Exp $"
#endif #endif
# include "vvp_priv.h" # include "vvp_priv.h"
@ -147,9 +147,6 @@ static int compare_exp(ivl_expr_t l, ivl_expr_t r)
if (ivl_expr_signal(l) != ivl_expr_signal(r)) if (ivl_expr_signal(l) != ivl_expr_signal(r))
return 0; return 0;
if (ivl_expr_lsi(l) != ivl_expr_lsi(r))
return 0;
if (ivl_expr_width(l) != ivl_expr_width(r)) if (ivl_expr_width(l) != ivl_expr_width(r))
return 0; return 0;
@ -211,6 +208,9 @@ unsigned allocate_vector_exp(ivl_expr_t exp, unsigned wid)
/* /*
* $Log: vector.c,v $ * $Log: vector.c,v $
* Revision 1.5 2005/01/24 05:08:02 steve
* Part selects are done in the compiler, not here.
*
* Revision 1.4 2003/07/03 17:44:10 steve * Revision 1.4 2003/07/03 17:44:10 steve
* Wider thread vector limit. * Wider thread vector limit.
* *