While loops

tgt-vhdl/stmt.cc

@@ -412,6 +412,21 @@ static int draw_case(vhdl_process *proc, stmt_container *container,
    return 0;
 }
 
+int draw_while(vhdl_process *proc, stmt_container *container,
+               ivl_statement_t stmt)
+{
+   vhdl_expr *test = translate_expr(ivl_stmt_cond_expr(stmt));
+   if (NULL == test)
+      return 1;
+
+   vhdl_while_stmt *loop = new vhdl_while_stmt(test);
+   container->add_stmt(loop);
+
+   draw_stmt(proc, loop->get_container(), ivl_stmt_sub_stmt(stmt));
+   
+   return 0;
+}
+
 /*
  * Generate VHDL statements for the given Verilog statement and
  * add them to the given VHDL process. The container is the
@@ -443,6 +458,8 @@ int draw_stmt(vhdl_process *proc, stmt_container *container,
       return draw_if(proc, container, stmt);
    case IVL_ST_CASE:
       return draw_case(proc, container, stmt);
+   case IVL_ST_WHILE:
+      return draw_while(proc, container, stmt);
    default:
       error("No VHDL translation for statement at %s:%d (type = %d)",
             ivl_stmt_file(stmt), ivl_stmt_lineno(stmt),

tgt-vhdl/vhdl_syntax.cc

@@ -776,6 +776,22 @@ void vhdl_case_stmt::emit(std::ofstream &of, int level) const
    of << "end case;";
 }
 
+vhdl_while_stmt::~vhdl_while_stmt()
+{
+   delete test_;
+}
+
+void vhdl_while_stmt::emit(std::ofstream &of, int level) const
+{
+   of << "while ";
+   test_->emit(of, level);
+   of << " loop";
+   stmts_.emit(of, indent(level));
+   of << "end loop;";
+}
+
+
+
 
 
 

tgt-vhdl/vhdl_syntax.hh

@@ -364,6 +364,19 @@ private:
 };
 
 
+class vhdl_while_stmt : public vhdl_seq_stmt {
+public:
+   vhdl_while_stmt(vhdl_expr *test) : test_(test) {}
+   ~vhdl_while_stmt();
+
+   stmt_container *get_container() { return &stmts_; }
+   void emit(std::ofstream &of, int level) const;
+private:
+   vhdl_expr *test_;
+   stmt_container stmts_;
+};
+
+
 /*
  * A procedure call. Which is a statement, unlike a function
  * call which is an expression.