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More xilinx common code.

This commit is contained in:
steve 2003-07-02 03:02:15 +00:00
parent b810556d3f
commit eb605694eb
4 changed files with 124 additions and 156 deletions
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99
tgt-fpga/d-virtex.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: d-virtex.c,v 1.29 2003/07/02 02:58:18 steve Exp $" #ident "$Id: d-virtex.c,v 1.30 2003/07/02 03:02:15 steve Exp $"
#endif #endif
# include "device.h" # include "device.h"
@ -53,66 +53,9 @@ const static struct edif_xlib_celltable virtex_celltable[] = {
*/ */
static void virtex_show_header(ivl_design_t des) static void virtex_show_header(ivl_design_t des)
{ {
unsigned idx;
ivl_scope_t root = ivl_design_root(des);
unsigned sig_cnt = ivl_scope_sigs(root);
unsigned nports = 0, pidx;
const char*part_str = 0; const char*part_str = 0;
/* Count the ports I'm going to use. */ xilinx_common_header(des);
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
nports += ivl_signal_pins(sig);
}
edf = edif_create(ivl_scope_basename(root), nports);
pidx = 0;
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
edif_joint_t jnt;
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
if (ivl_signal_pins(sig) == 1) {
edif_portconfig(edf, pidx, ivl_signal_basename(sig),
ivl_signal_port(sig));
assert(ivl_signal_pins(sig) == 1);
jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
edif_port_to_joint(jnt, edf, pidx);
} else {
const char*name = ivl_signal_basename(sig);
ivl_signal_port_t dir = ivl_signal_port(sig);
char buf[128];
unsigned bit;
for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
const char*tmp;
sprintf(buf, "%s[%u]", name, bit);
tmp = strdup(buf);
edif_portconfig(edf, pidx+bit, tmp, dir);
jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
edif_port_to_joint(jnt, edf, pidx+bit);
}
}
pidx += ivl_signal_pins(sig);
}
assert(pidx == nports);
xlib = edif_xlibrary_create(edf, "VIRTEX"); xlib = edif_xlibrary_create(edf, "VIRTEX");
edif_xlibrary_set_celltable(xlib, virtex_celltable); edif_xlibrary_set_celltable(xlib, virtex_celltable);
@ -130,39 +73,6 @@ static void virtex_show_header(ivl_design_t des)
} }
void virtex_show_footer(ivl_design_t des)
{
unsigned idx;
for (idx = 0 ; idx < ivl_design_consts(des) ; idx += 1) {
unsigned pin;
ivl_net_const_t net = ivl_design_const(des, idx);
const char*val = ivl_const_bits(net);
for (pin = 0 ; pin < ivl_const_pins(net) ; pin += 1) {
edif_joint_t jnt;
edif_cellref_t pad;
jnt = edif_joint_of_nexus(edf, ivl_const_pin(net, pin));
switch (val[pin]) {
case '0':
pad = edif_cellref_create(edf, cell_0);
break;
case '1':
pad = edif_cellref_create(edf, cell_1);
break;
default:
assert(0);
break;
}
edif_add_to_joint(jnt, pad, 0);
}
}
edif_print(xnf, edf);
}
static void virtex_or_wide(ivl_net_logic_t net) static void virtex_or_wide(ivl_net_logic_t net)
{ {
edif_cell_t cell_muxcy_l = xilinx_cell_muxcy_l(xlib); edif_cell_t cell_muxcy_l = xilinx_cell_muxcy_l(xlib);
@ -832,7 +742,7 @@ void virtex_add(ivl_lpm_t net)
const struct device_s d_virtex_edif = { const struct device_s d_virtex_edif = {
virtex_show_header, virtex_show_header,
virtex_show_footer, xilinx_show_footer,
xilinx_show_scope, xilinx_show_scope,
xilinx_pad, xilinx_pad,
virtex_logic, virtex_logic,
@ -850,6 +760,9 @@ const struct device_s d_virtex_edif = {
/* /*
* $Log: d-virtex.c,v $ * $Log: d-virtex.c,v $
* Revision 1.30 2003/07/02 03:02:15 steve
* More xilinx common code.
*
* Revision 1.29 2003/07/02 02:58:18 steve * Revision 1.29 2003/07/02 02:58:18 steve
* Remember to set INIT on wide-or trailing luts. * Remember to set INIT on wide-or trailing luts.
* *

66
tgt-fpga/d-virtex2.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: d-virtex2.c,v 1.16 2003/06/28 04:18:47 steve Exp $" #ident "$Id: d-virtex2.c,v 1.17 2003/07/02 03:02:15 steve Exp $"
#endif #endif
# include "device.h" # include "device.h"
@ -54,66 +54,9 @@ const static struct edif_xlib_celltable virtex2_celltable[] = {
*/ */
static void virtex2_show_header(ivl_design_t des) static void virtex2_show_header(ivl_design_t des)
{ {
unsigned idx;
ivl_scope_t root = ivl_design_root(des);
unsigned sig_cnt = ivl_scope_sigs(root);
unsigned nports = 0, pidx;
const char*part_str = 0; const char*part_str = 0;
/* Count the ports I'm going to use. */ xilinx_common_header(des);
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
nports += ivl_signal_pins(sig);
}
edf = edif_create(ivl_scope_basename(root), nports);
pidx = 0;
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
edif_joint_t jnt;
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
if (ivl_signal_pins(sig) == 1) {
edif_portconfig(edf, pidx, ivl_signal_basename(sig),
ivl_signal_port(sig));
assert(ivl_signal_pins(sig) == 1);
jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
edif_port_to_joint(jnt, edf, pidx);
} else {
const char*name = ivl_signal_basename(sig);
ivl_signal_port_t dir = ivl_signal_port(sig);
char buf[128];
unsigned bit;
for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
const char*tmp;
sprintf(buf, "%s[%u]", name, bit);
tmp = strdup(buf);
edif_portconfig(edf, pidx+bit, tmp, dir);
jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
edif_port_to_joint(jnt, edf, pidx+bit);
}
}
pidx += ivl_signal_pins(sig);
}
assert(pidx == nports);
xlib = edif_xlibrary_create(edf, "VIRTEX2"); xlib = edif_xlibrary_create(edf, "VIRTEX2");
edif_xlibrary_set_celltable(xlib, virtex2_celltable); edif_xlibrary_set_celltable(xlib, virtex2_celltable);
@ -133,7 +76,7 @@ static void virtex2_show_header(ivl_design_t des)
const struct device_s d_virtex2_edif = { const struct device_s d_virtex2_edif = {
virtex2_show_header, virtex2_show_header,
virtex_show_footer, xilinx_show_footer,
xilinx_show_scope, xilinx_show_scope,
xilinx_pad, xilinx_pad,
virtex_logic, virtex_logic,
@ -151,6 +94,9 @@ const struct device_s d_virtex2_edif = {
/* /*
* $Log: d-virtex2.c,v $ * $Log: d-virtex2.c,v $
* Revision 1.17 2003/07/02 03:02:15 steve
* More xilinx common code.
*
* Revision 1.16 2003/06/28 04:18:47 steve * Revision 1.16 2003/06/28 04:18:47 steve
* Add support for wide OR/NOR gates. * Add support for wide OR/NOR gates.
* *

107
tgt-fpga/xilinx.c
View File

@ -17,12 +17,13 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: xilinx.c,v 1.5 2003/07/02 00:25:40 steve Exp $" #ident "$Id: xilinx.c,v 1.6 2003/07/02 03:02:15 steve Exp $"
#endif #endif
# include "edif.h" # include "edif.h"
# include "generic.h" # include "generic.h"
# include "xilinx.h" # include "xilinx.h"
# include "fpga_priv.h"
# include <stdlib.h> # include <stdlib.h>
# include <string.h> # include <string.h>
#ifdef HAVE_MALLOC_H #ifdef HAVE_MALLOC_H
@ -230,6 +231,107 @@ edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
return cell; return cell;
} }
/*
* This function does a lot of the stuff common to the header
* functions of various Xilinx familes. This includes creating the edf
* object that holds the netlist.
*/
void xilinx_common_header(ivl_design_t des)
{
unsigned idx;
ivl_scope_t root = ivl_design_root(des);
unsigned sig_cnt = ivl_scope_sigs(root);
unsigned nports = 0, pidx;
/* Count the ports I'm going to use. */
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
nports += ivl_signal_pins(sig);
}
edf = edif_create(ivl_scope_basename(root), nports);
pidx = 0;
for (idx = 0 ; idx < sig_cnt ; idx += 1) {
edif_joint_t jnt;
ivl_signal_t sig = ivl_scope_sig(root, idx);
if (ivl_signal_port(sig) == IVL_SIP_NONE)
continue;
if (ivl_signal_attr(sig, "PAD") != 0)
continue;
if (ivl_signal_pins(sig) == 1) {
edif_portconfig(edf, pidx, ivl_signal_basename(sig),
ivl_signal_port(sig));
assert(ivl_signal_pins(sig) == 1);
jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
edif_port_to_joint(jnt, edf, pidx);
} else {
const char*name = ivl_signal_basename(sig);
ivl_signal_port_t dir = ivl_signal_port(sig);
char buf[128];
unsigned bit;
for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
const char*tmp;
sprintf(buf, "%s[%u]", name, bit);
tmp = strdup(buf);
edif_portconfig(edf, pidx+bit, tmp, dir);
jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
edif_port_to_joint(jnt, edf, pidx+bit);
}
}
pidx += ivl_signal_pins(sig);
}
assert(pidx == nports);
}
void xilinx_show_footer(ivl_design_t des)
{
unsigned idx;
for (idx = 0 ; idx < ivl_design_consts(des) ; idx += 1) {
unsigned pin;
ivl_net_const_t net = ivl_design_const(des, idx);
const char*val = ivl_const_bits(net);
for (pin = 0 ; pin < ivl_const_pins(net) ; pin += 1) {
edif_joint_t jnt;
edif_cellref_t pad;
jnt = edif_joint_of_nexus(edf, ivl_const_pin(net, pin));
switch (val[pin]) {
case '0':
pad = edif_cellref_create(edf, cell_0);
break;
case '1':
pad = edif_cellref_create(edf, cell_1);
break;
default:
assert(0);
break;
}
edif_add_to_joint(jnt, pad, 0);
}
}
edif_print(xnf, edf);
}
/* /*
* Make (or retrieve) a cell in the external library that reflects the * Make (or retrieve) a cell in the external library that reflects the
* scope with its ports. * scope with its ports.
@ -792,6 +894,9 @@ void xilinx_shiftl(ivl_lpm_t net)
/* /*
* $Log: xilinx.c,v $ * $Log: xilinx.c,v $
* Revision 1.6 2003/07/02 03:02:15 steve
* More xilinx common code.
*
* Revision 1.5 2003/07/02 00:25:40 steve * Revision 1.5 2003/07/02 00:25:40 steve
* Add xilinx support for bufif1. * Add xilinx support for bufif1.
* *

8
tgt-fpga/xilinx.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: xilinx.h,v 1.5 2003/07/02 00:25:40 steve Exp $" #ident "$Id: xilinx.h,v 1.6 2003/07/02 03:02:15 steve Exp $"
#endif #endif
/* /*
@ -98,13 +98,14 @@ extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
/* === Inheritable Methods === */ /* === Inheritable Methods === */
extern void virtex_show_footer(ivl_design_t des);
extern void virtex_logic(ivl_net_logic_t net); extern void virtex_logic(ivl_net_logic_t net);
extern void virtex_generic_dff(ivl_lpm_t net); extern void virtex_generic_dff(ivl_lpm_t net);
extern void virtex_eq(ivl_lpm_t net); extern void virtex_eq(ivl_lpm_t net);
extern void virtex_ge(ivl_lpm_t net); extern void virtex_ge(ivl_lpm_t net);
extern void virtex_add(ivl_lpm_t net); extern void virtex_add(ivl_lpm_t net);
extern void xilinx_common_header(ivl_design_t des);
extern void xilinx_show_footer(ivl_design_t des);
extern void xilinx_show_scope(ivl_scope_t scope); extern void xilinx_show_scope(ivl_scope_t scope);
extern void xilinx_pad(ivl_signal_t, const char*str); extern void xilinx_pad(ivl_signal_t, const char*str);
extern void xilinx_logic(ivl_net_logic_t net); extern void xilinx_logic(ivl_net_logic_t net);
@ -114,6 +115,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
/* /*
* $Log: xilinx.h,v $ * $Log: xilinx.h,v $
* Revision 1.6 2003/07/02 03:02:15 steve
* More xilinx common code.
*
* Revision 1.5 2003/07/02 00:25:40 steve * Revision 1.5 2003/07/02 00:25:40 steve
* Add xilinx support for bufif1. * Add xilinx support for bufif1.
* *