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Spelling fixes.

This commit is contained in:
steve 2003-01-30 16:23:07 +00:00
parent 8f4afd53a6
commit e941e7e805
33 changed files with 167 additions and 86 deletions
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7
BUGS.txt
View File

@ -16,7 +16,7 @@ compilation tools you are using. Specifically, I need to know:
- Operating system and processor type, - Operating system and processor type,
- Compiler w/ version, - Compiler w/ version,
- Library version, and - Library version, and
- anything else you think relevent. - anything else you think relevant.
Be aware that I do not have at my disposal a porting lab. I have the Be aware that I do not have at my disposal a porting lab. I have the
alpha on my desk, and the Linux/Intel box with a logic analyzer and alpha on my desk, and the Linux/Intel box with a logic analyzer and
@ -141,8 +141,11 @@ then falls under the "otherwise noted" category.
I must insist that any copyright material submitted for inclusion I must insist that any copyright material submitted for inclusion
include the GPL license notice as shown in the rest of the source. include the GPL license notice as shown in the rest of the source.
$Id: BUGS.txt,v 1.2 1999/08/06 04:05:28 steve Exp $ $Id: BUGS.txt,v 1.3 2003/01/30 16:23:07 steve Exp $
$Log: BUGS.txt,v $ $Log: BUGS.txt,v $
Revision 1.3 2003/01/30 16:23:07 steve
Spelling fixes.
Revision 1.2 1999/08/06 04:05:28 steve Revision 1.2 1999/08/06 04:05:28 steve
Handle scope of parameters. Handle scope of parameters.

7
PEvent.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: PEvent.h,v 1.6 2002/08/12 01:34:58 steve Exp $" #ident "$Id: PEvent.h,v 1.7 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "LineInfo.h" # include "LineInfo.h"
@ -31,7 +31,7 @@ class NetScope;
/* /*
* The PEvent class represents event objects. These are things that * The PEvent class represents event objects. These are things that
* are declared in Verilog as ``event foo;'' The name passed to the * are declared in Verilog as ``event foo;'' The name passed to the
* constructure is the "foo" part of the declaration. * constructor is the "foo" part of the declaration.
*/ */
class PEvent : public LineInfo { class PEvent : public LineInfo {
@ -53,6 +53,9 @@ class PEvent : public LineInfo {
/* /*
* $Log: PEvent.h,v $ * $Log: PEvent.h,v $
* Revision 1.7 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.6 2002/08/12 01:34:58 steve * Revision 1.6 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig. * conditional ident string using autoconfig.
* *

9
PExpr.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: PExpr.h,v 1.63 2002/11/09 19:20:48 steve Exp $" #ident "$Id: PExpr.h,v 1.64 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include <string> # include <string>
@ -51,7 +51,7 @@ class PExpr : public LineInfo {
virtual void dump(ostream&) const; virtual void dump(ostream&) const;
// Procedural elaboration of the expression. Set thie // Procedural elaboration of the expression. Set the
// bare_memory_ok flag if the result is allowed to be a // bare_memory_ok flag if the result is allowed to be a
// NetEMemory without an index. // NetEMemory without an index.
virtual NetExpr*elaborate_expr(Design*des, NetScope*scope, virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
@ -105,7 +105,7 @@ class PExpr : public LineInfo {
// Return true if this expression is a valid constant // Return true if this expression is a valid constant
// expression. the Module pointer is needed to find parameter // expression. the Module pointer is needed to find parameter
// identifiers and any other module specific interpretations // identifiers and any other module specific interpretations
// of expresions. // of expressions.
virtual bool is_constant(Module*) const; virtual bool is_constant(Module*) const;
private: // not implemented private: // not implemented
@ -504,6 +504,9 @@ class PECallFunction : public PExpr {
/* /*
* $Log: PExpr.h,v $ * $Log: PExpr.h,v $
* Revision 1.64 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.63 2002/11/09 19:20:48 steve * Revision 1.63 2002/11/09 19:20:48 steve
* Port expressions for output ports are lnets, not nets. * Port expressions for output ports are lnets, not nets.
* *

7
PUdp.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: PUdp.h,v 1.7 2002/08/12 01:34:58 steve Exp $" #ident "$Id: PUdp.h,v 1.8 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include <map> # include <map>
@ -53,7 +53,7 @@ svector<string>::svector<string>(unsigned size)
* the current output. * the current output.
* *
* If the UDP is sequential, the "initial" member is taken to be the * If the UDP is sequential, the "initial" member is taken to be the
* intial value assigned in the source, or 'x' if none is given. * initial value assigned in the source, or 'x' if none is given.
*/ */
class PUdp { class PUdp {
@ -84,6 +84,9 @@ class PUdp {
/* /*
* $Log: PUdp.h,v $ * $Log: PUdp.h,v $
* Revision 1.8 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.7 2002/08/12 01:34:58 steve * Revision 1.7 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig. * conditional ident string using autoconfig.
* *

7
PWire.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: PWire.h,v 1.15 2003/01/26 21:15:58 steve Exp $" #ident "$Id: PWire.h,v 1.16 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -38,7 +38,7 @@ class Design;
/* /*
* Wires include nets, registers and ports. A net or register becomes * Wires include nets, registers and ports. A net or register becomes
* a port by declaration, so ports are not seperate. The module * a port by declaration, so ports are not separate. The module
* identifies a port by keeping it in its port list. * identifies a port by keeping it in its port list.
* *
* The hname parameter to the constructor is a hierarchical name. It * The hname parameter to the constructor is a hierarchical name. It
@ -100,6 +100,9 @@ class PWire : public LineInfo {
/* /*
* $Log: PWire.h,v $ * $Log: PWire.h,v $
* Revision 1.16 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.15 2003/01/26 21:15:58 steve * Revision 1.15 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

2
QUICK_START.txt
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@ -79,5 +79,5 @@ Verilog packages from the main Debian software site.
* Install From Source * Install From Source
In this case, see the readme and other documentation that comes with In this case, see README.txt and other documentation that comes with
the source. the source.

4
README.txt
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@ -13,7 +13,7 @@ home page at <http://www.icarus.com/eda/verilog>.
Icarus Verilog is not aimed at being a simulator in the traditional Icarus Verilog is not aimed at being a simulator in the traditional
sense, but a compiler that generates code employed by back-end sense, but a compiler that generates code employed by back-end
tools. These back-end tools currently include a simulator engine tools. These back-end tools currently include a simulator engine
called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF fpga called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF FPGA
netlist generator. In the future, backends are expected for EDIF/LPM, netlist generator. In the future, backends are expected for EDIF/LPM,
structural Verilog, VHDL, etc. structural Verilog, VHDL, etc.
@ -363,7 +363,7 @@ language that are defined.
can theoretically be evaluated at compile time, instead of can theoretically be evaluated at compile time, instead of
using runtime VPI code. Doing so means that VPI cannot using runtime VPI code. Doing so means that VPI cannot
override the definitions of functions handled in this override the definitions of functions handled in this
manner. On the other hand, this makes them synthesizeable, and manner. On the other hand, this makes them synthesizable, and
also allows for more aggressive constant propagation. The also allows for more aggressive constant propagation. The
functions handled in this manner are: functions handled in this manner are:

7
Statement.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: Statement.h,v 1.36 2002/08/12 01:34:58 steve Exp $" #ident "$Id: Statement.h,v 1.37 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include <string> # include <string>
@ -287,7 +287,7 @@ class PDelayStatement : public Statement {
/* /*
* This represends the parsing of a disable <scope> statement. * This represents the parsing of a disable <scope> statement.
*/ */
class PDisable : public Statement { class PDisable : public Statement {
@ -453,6 +453,9 @@ class PWhile : public Statement {
/* /*
* $Log: Statement.h,v $ * $Log: Statement.h,v $
* Revision 1.37 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.36 2002/08/12 01:34:58 steve * Revision 1.36 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig. * conditional ident string using autoconfig.
* *

4
attributes.txt
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@ -28,14 +28,14 @@ warning.)
(* ivl_synthesis_on *) (* ivl_synthesis_on *)
This attribute tells the compiler that the marked always statement This attribute tells the compiler that the marked always statement
is synthesizeable. The compiler will attempt to synthesize the is synthesizable. The compiler will attempt to synthesize the
code in the marked "always" statement. If it cannot in any way code in the marked "always" statement. If it cannot in any way
synthesize it, then it will report an error. synthesize it, then it will report an error.
(* ivl_synthesis_off *) (* ivl_synthesis_off *)
If this value is attached to an "always" statement, then the If this value is attached to an "always" statement, then the
compiler will *not* synthesize the "always" statment. This can be compiler will *not* synthesize the "always" statement. This can be
used, for example, to mark embedded test bench code. used, for example, to mark embedded test bench code.

9
compiler.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: compiler.h,v 1.13 2002/08/12 01:34:58 steve Exp $" #ident "$Id: compiler.h,v 1.14 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include <list> # include <list>
@ -69,13 +69,13 @@
extern bool warn_implicit; extern bool warn_implicit;
extern bool error_implicit; extern bool error_implicit;
/* inherit timescales accross files. */ /* inherit timescales across files. */
extern bool warn_timescale; extern bool warn_timescale;
/* This is true if verbose output is requested. */ /* This is true if verbose output is requested. */
extern bool verbose_flag; extern bool verbose_flag;
/* This is an ordered list of library suffixxes to search. */ /* This is an ordered list of library suffixes to search. */
extern list<const char*>library_suff; extern list<const char*>library_suff;
extern int build_library_index(const char*path, bool key_case_sensitive); extern int build_library_index(const char*path, bool key_case_sensitive);
@ -95,6 +95,9 @@ extern char*ivlpp_string;
/* /*
* $Log: compiler.h,v $ * $Log: compiler.h,v $
* Revision 1.14 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.13 2002/08/12 01:34:58 steve * Revision 1.13 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig. * conditional ident string using autoconfig.
* *

9
cprop.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: cprop.cc,v 1.40 2003/01/27 05:09:17 steve Exp $" #ident "$Id: cprop.cc,v 1.41 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -806,7 +806,7 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
} }
/* /*
* This detects the case where the mux selects between a value an * This detects the case where the mux selects between a value and
* Vz. In this case, replace the device with a bufif with the sel * Vz. In this case, replace the device with a bufif with the sel
* input used to enable the output. * input used to enable the output.
*/ */
@ -980,7 +980,7 @@ void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
void cprop(Design*des) void cprop(Design*des)
{ {
// Continually propogate constants until a scan finds nothing // Continually propagate constants until a scan finds nothing
// to do. // to do.
cprop_functor prop; cprop_functor prop;
do { do {
@ -994,6 +994,9 @@ void cprop(Design*des)
/* /*
* $Log: cprop.cc,v $ * $Log: cprop.cc,v $
* Revision 1.41 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.40 2003/01/27 05:09:17 steve * Revision 1.40 2003/01/27 05:09:17 steve
* Spelling fixes. * Spelling fixes.
* *

8
cygwin.txt
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@ -1,6 +1,12 @@
This file describes the build procedure under cygwin32 (Windows 95/98/NT/2K) This file describes the build procedure under cygwin32 (Windows 95/98/NT/2K)
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
Note: Icarus Verilog also compiles to native Windows binaries if you
use the instructions in the mingw.txt file. Some people prefer cygwin
binaries, and these instructions apply.
To build using cygwin: To build using cygwin:
Prerequisites: Prerequisites:
@ -8,7 +14,7 @@ Prerequisites:
o Latest net release (1.1.4) of cygwin (sources.redhat.com/cygwin) o Latest net release (1.1.4) of cygwin (sources.redhat.com/cygwin)
Procedure: Procedure:
o Get the source code - see the main icarus verilog page for how to o Get the source code - see the main Icarus Verilog page for how to
do this do this
o cd to the verilog directory o cd to the verilog directory
o autoconf.sh o autoconf.sh

7
elab_sig.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: elab_sig.cc,v 1.26 2003/01/27 05:09:17 steve Exp $" #ident "$Id: elab_sig.cc,v 1.27 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -525,6 +525,9 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
/* /*
* $Log: elab_sig.cc,v $ * $Log: elab_sig.cc,v $
* Revision 1.27 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.26 2003/01/27 05:09:17 steve * Revision 1.26 2003/01/27 05:09:17 steve
* Spelling fixes. * Spelling fixes.
* *
@ -619,7 +622,7 @@ void PWire::elaborate_sig(Design*des, NetScope*scope) const
* for regs that are not really values. * for regs that are not really values.
* *
* Revision 1.1 2000/05/02 16:27:38 steve * Revision 1.1 2000/05/02 16:27:38 steve
* Move signal elaboration to a seperate pass. * Move signal elaboration to a separate pass.
* *
*/ */

11
elaborate.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: elaborate.cc,v 1.270 2003/01/27 05:09:17 steve Exp $" #ident "$Id: elaborate.cc,v 1.271 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -285,7 +285,7 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
} }
/* Allocate all the getlist nodes for the gates. */ /* Allocate all the netlist nodes for the gates. */
NetLogic**cur = new NetLogic*[count]; NetLogic**cur = new NetLogic*[count];
assert(cur); assert(cur);
@ -1780,7 +1780,7 @@ NetProc* PEventStatement::elaborate_st(Design*des, NetScope*scope,
<statement> <statement>
end end
This is equivalent, and uses the existing capapilities of This is equivalent, and uses the existing capabilities of
the netlist format. The resulting netlist should look like the netlist format. The resulting netlist should look like
this: this:
@ -2467,7 +2467,7 @@ Design* elaborate(list<const char*>roots)
des->run_defparams(); des->run_defparams();
// At this point, all parameter overrides are done. Scane the // At this point, all parameter overrides are done. Scan the
// scopes and evaluate the parameters all the way down to // scopes and evaluate the parameters all the way down to
// constants. // constants.
des->evaluate_parameters(); des->evaluate_parameters();
@ -2507,6 +2507,9 @@ Design* elaborate(list<const char*>roots)
/* /*
* $Log: elaborate.cc,v $ * $Log: elaborate.cc,v $
* Revision 1.271 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.270 2003/01/27 05:09:17 steve * Revision 1.270 2003/01/27 05:09:17 steve
* Spelling fixes. * Spelling fixes.
* *

7
eval_tree.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: eval_tree.cc,v 1.45 2003/01/27 05:09:17 steve Exp $" #ident "$Id: eval_tree.cc,v 1.46 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -523,7 +523,7 @@ NetEConst* NetEBComp::eval_tree()
case 'L': // <= case 'L': // <=
return eval_leeq_(); return eval_leeq_();
case 'N': // Cse inequality (!==) case 'N': // Case inequality (!==)
return eval_neeqeq_(); return eval_neeqeq_();
case 'n': // not-equal (!=) case 'n': // not-equal (!=)
@ -1187,6 +1187,9 @@ NetEConst* NetEUReduce::eval_tree()
/* /*
* $Log: eval_tree.cc,v $ * $Log: eval_tree.cc,v $
* Revision 1.46 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.45 2003/01/27 05:09:17 steve * Revision 1.45 2003/01/27 05:09:17 steve
* Spelling fixes. * Spelling fixes.
* *

7
expr_synth.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: expr_synth.cc,v 1.38 2003/01/26 21:15:58 steve Exp $" #ident "$Id: expr_synth.cc,v 1.39 2003/01/30 16:23:07 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -455,7 +455,7 @@ NetNet* NetEConst::synthesize(Design*des)
NetNet* NetECReal::synthesize(Design*des) NetNet* NetECReal::synthesize(Design*des)
{ {
cerr << get_line() << ": error: Real constants are " cerr << get_line() << ": error: Real constants are "
<< "not synthesizeable." << endl; << "not synthesizable." << endl;
des->errors += 1; des->errors += 1;
return 0; return 0;
} }
@ -643,6 +643,9 @@ NetNet* NetESignal::synthesize(Design*des)
/* /*
* $Log: expr_synth.cc,v $ * $Log: expr_synth.cc,v $
* Revision 1.39 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.38 2003/01/26 21:15:58 steve * Revision 1.38 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

9
ivl_target.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_target.h,v 1.110 2003/01/26 21:15:58 steve Exp $" #ident "$Id: ivl_target.h,v 1.111 2003/01/30 16:23:07 steve Exp $"
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
@ -438,7 +438,7 @@ extern ivl_nexus_t ivl_event_pos(ivl_event_t net, unsigned idx);
* *
* ivl_expr_opcode * ivl_expr_opcode
* IVL_EX_BINARY and IVL_EX_UNARY expression nodes include an * IVL_EX_BINARY and IVL_EX_UNARY expression nodes include an
* upcode from this table: * opcode from this table:
* & -- AND * & -- AND
* A -- NAND (~&) * A -- NAND (~&)
* X -- XNOR (~^) * X -- XNOR (~^)
@ -968,7 +968,7 @@ extern int ivl_scope_time_units(ivl_scope_t net);
* This function returns the fully scoped hierarchical name for the * This function returns the fully scoped hierarchical name for the
* signal. The name refers to the entire vector that is the signal. * signal. The name refers to the entire vector that is the signal.
* *
* NOTE: This function is deprecated. The heirarchical name is too * NOTE: This function is deprecated. The hierarchical name is too
* vague a construct when escaped names can have . characters in * vague a construct when escaped names can have . characters in
* them. Do no use this function in new code, it will disappear. * them. Do no use this function in new code, it will disappear.
* *
@ -1143,6 +1143,9 @@ _END_DECL
/* /*
* $Log: ivl_target.h,v $ * $Log: ivl_target.h,v $
* Revision 1.111 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.110 2003/01/26 21:15:58 steve * Revision 1.110 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

2
lpm.txt
View File

@ -1,7 +1,7 @@
WHAT IS LPM WHAT IS LPM
LPM (Library of Paramaterized Modules) is EIS-IS standard 103-A. It is LPM (Library of Parameterized Modules) is EIS-IS standard 103-A. It is
a standard library of abstract devices that are designed to be close a standard library of abstract devices that are designed to be close
enough to the target hardware to be easily translated, yet abstract enough to the target hardware to be easily translated, yet abstract
enough to support a variety of target technologies without excessive enough to support a variety of target technologies without excessive

2
mingw.txt
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@ -6,7 +6,7 @@ MINGW PORT OF ICARUS VERILOG
Icarus Verilog source can be compiled with the mingw C/C++ compilers Icarus Verilog source can be compiled with the mingw C/C++ compilers
to get a Windows binary that does not require the posix compatibility to get a Windows binary that does not require the POSIX compatibility
cruft of the Cygwin.dll library. The configure scripts automatically cruft of the Cygwin.dll library. The configure scripts automatically
detect that the compilers in use are the mingw compilers and will detect that the compilers in use are the mingw compilers and will
configure the Makefiles appropriately. configure the Makefiles appropriately.

33
netlist.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.h,v 1.273 2003/01/27 00:14:37 steve Exp $" #ident "$Id: netlist.h,v 1.274 2003/01/30 16:23:08 steve Exp $"
#endif #endif
/* /*
@ -908,13 +908,13 @@ class NetUserFunc : public NetNode {
/* ========= /* =========
* There are cases where expressions need to be represented. The * There are cases where expressions need to be represented. The
* NetExpr class is the root of a heirarchy that serves that purpose. * NetExpr class is the root of a hierarchy that serves that purpose.
* *
* The expr_width() is the width of the expression, that accounts * The expr_width() is the width of the expression, that accounts
* for the widths of the sub-expressions I might have. It is up to the * for the widths of the sub-expressions I might have. It is up to the
* derived classes to properly set the expr width, if need be. The * derived classes to properly set the expr width, if need be. The
* set_width() method is used to compel an expression to have a * set_width() method is used to compel an expression to have a
* certain width, and is used particulary when the expression is an * certain width, and is used particularly when the expression is an
* rvalue in an assignment statement. * rvalue in an assignment statement.
*/ */
class NetExpr : public LineInfo { class NetExpr : public LineInfo {
@ -939,7 +939,7 @@ class NetExpr : public LineInfo {
unsigned expr_width() const { return width_; } unsigned expr_width() const { return width_; }
// Coerce the expression to have a specific width. If the // Coerce the expression to have a specific width. If the
// coersion works, then return true. Otherwise, return false. // coercion works, then return true. Otherwise, return false.
virtual bool set_width(unsigned); virtual bool set_width(unsigned);
// This method returns true if the expression is // This method returns true if the expression is
@ -959,7 +959,7 @@ class NetExpr : public LineInfo {
// This method evaluates the expression and returns an // This method evaluates the expression and returns an
// equivilent expression that is reduced as far as compile // equivalent expression that is reduced as far as compile
// time knows how. Essentially, this is designed to fold // time knows how. Essentially, this is designed to fold
// constants. // constants.
virtual NetExpr*eval_tree(); virtual NetExpr*eval_tree();
@ -1075,7 +1075,7 @@ class NetBUFZ : public NetNode {
/* /*
* This node is used to represent case equality in combinational * This node is used to represent case equality in combinational
* logic. Although this is not normally synthesizeable, it makes sense * logic. Although this is not normally synthesizable, it makes sense
* to support an abstract gate that can compare x and z. * to support an abstract gate that can compare x and z.
* *
* This pins are assigned as: * This pins are assigned as:
@ -1671,7 +1671,7 @@ class NetDisable : public NetProc {
* event or trigger the event. Event waits refer to this object, as do * event or trigger the event. Event waits refer to this object, as do
* the event trigger statements. The NetEvent class may have a name and * the event trigger statements. The NetEvent class may have a name and
* a scope. The name is a simple name (no hierarchy) and the scope is * a scope. The name is a simple name (no hierarchy) and the scope is
* the NetScope that contains the object. The socpe member is written * the NetScope that contains the object. The scope member is written
* by the NetScope object when the NetEvent is stored. * by the NetScope object when the NetEvent is stored.
* *
* The NetEvWait class represents a thread wait for an event. When * The NetEvWait class represents a thread wait for an event. When
@ -1685,7 +1685,7 @@ class NetDisable : public NetProc {
* turn awakens the waiting threads. Each NetEvTrig object references * turn awakens the waiting threads. Each NetEvTrig object references
* exactly one event object. * exactly one event object.
* *
* The NetEvProbe class is the structural equivilent of the NetEvTrig, * The NetEvProbe class is the structural equivalent of the NetEvTrig,
* in that it is a node and watches bit values that it receives. It * in that it is a node and watches bit values that it receives. It
* checks for edges then if appropriate triggers the associated * checks for edges then if appropriate triggers the associated
* NetEvent. Each NetEvProbe references exactly one event object, and * NetEvent. Each NetEvProbe references exactly one event object, and
@ -2054,8 +2054,8 @@ class NetSTask : public NetProc {
* The task also introduces a scope, and the parameters are actually * The task also introduces a scope, and the parameters are actually
* reg objects in the new scope. The task is called by the calling * reg objects in the new scope. The task is called by the calling
* thread assigning (blocking assignment) to the in and inout * thread assigning (blocking assignment) to the in and inout
* paramters, then invoking the thread, and finally assigning out the * parameters, then invoking the thread, and finally assigning out the
* output and inout variables. The variables accessable as ports are * output and inout variables. The variables accessible as ports are
* also elaborated and accessible as ordinary reg objects. * also elaborated and accessible as ordinary reg objects.
*/ */
class NetTaskDef { class NetTaskDef {
@ -2119,7 +2119,7 @@ class NetVariable : public LineInfo {
* *
* The NetNet parameter to the constructor is the *register* NetNet * The NetNet parameter to the constructor is the *register* NetNet
* that receives the result of the function, and the NetExpr list is * that receives the result of the function, and the NetExpr list is
* the paraneters passed to the function. * the parameters passed to the function.
*/ */
class NetEUFunc : public NetExpr { class NetEUFunc : public NetExpr {
@ -2541,9 +2541,9 @@ class NetEVariable : public NetExpr {
}; };
/* /*
* This clas is a placeholder for a parameter expression. When * This class is a placeholder for a parameter expression. When
* parameters are first created, an instance of this object is used to * parameters are first created, an instance of this object is used to
* hold the place where the parameter exression goes. Then, when the * hold the place where the parameter expression goes. Then, when the
* parameters are resolved, these objects are removed. * parameters are resolved, these objects are removed.
* *
* If the parameter object is created with a path and name, then the * If the parameter object is created with a path and name, then the
@ -2790,7 +2790,7 @@ class NetEMemory : public NetExpr {
* A signal shows up as a node in the netlist so that structural * A signal shows up as a node in the netlist so that structural
* activity can invoke the expression. This node also supports part * activity can invoke the expression. This node also supports part
* select by indexing a range of the NetNet that is associated with * select by indexing a range of the NetNet that is associated with
* it. The msi() is the mose significant index, and lsi() the least * it. The msi() is the more significant index, and lsi() the least
* significant index. * significant index.
*/ */
class NetESignal : public NetExpr { class NetESignal : public NetExpr {
@ -2873,7 +2873,7 @@ class NetScope {
/* Parameters exist within a scope, and these methods allow /* Parameters exist within a scope, and these methods allow
one to manipulate the set. In these cases, the name is the one to manipulate the set. In these cases, the name is the
*simple* name of the paramter, the heirarchy is implicit in *simple* name of the parameter, the hierarchy is implicit in
the scope. The return value from set_parameter is the the scope. The return value from set_parameter is the
previous expression, if there was one. */ previous expression, if there was one. */
@ -3191,6 +3191,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/* /*
* $Log: netlist.h,v $ * $Log: netlist.h,v $
* Revision 1.274 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.273 2003/01/27 00:14:37 steve * Revision 1.273 2003/01/27 00:14:37 steve
* Support in various contexts the $realtime * Support in various contexts the $realtime
* system task. * system task.

7
netmisc.h
View File

@ -19,13 +19,13 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: netmisc.h,v 1.16 2002/08/31 03:48:50 steve Exp $" #ident "$Id: netmisc.h,v 1.17 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
/* /*
* This funciton transforms an expression by padding the high bits * This function transforms an expression by padding the high bits
* with V0 until the expression has the desired width. This may mean * with V0 until the expression has the desired width. This may mean
* not transforming the expression at all, if it is already wide * not transforming the expression at all, if it is already wide
* enough. * enough.
@ -57,6 +57,9 @@ extern NetExpr* elab_and_eval(Design*des, NetScope*scope, const PExpr*pe);
/* /*
* $Log: netmisc.h,v $ * $Log: netmisc.h,v $
* Revision 1.17 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.16 2002/08/31 03:48:50 steve * Revision 1.16 2002/08/31 03:48:50 steve
* Fix reverse bit ordered bit select in continuous assignment. * Fix reverse bit ordered bit select in continuous assignment.
* *

7
pform.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: pform.h,v 1.65 2003/01/26 21:15:59 steve Exp $" #ident "$Id: pform.h,v 1.66 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -61,7 +61,7 @@ struct vlltype;
/* /*
* The min:typ:max expression s selected at parse time using the * The min:typ:max expression s selected at parse time using the
* enumeration. When the compiler makes a choise, it also prints a * enumeration. When the compiler makes a choice, it also prints a
* warning if min_typ_max_warn > 0. * warning if min_typ_max_warn > 0.
*/ */
extern enum MIN_TYP_MAX { MIN, TYP, MAX } min_typ_max_flag; extern enum MIN_TYP_MAX { MIN, TYP, MAX } min_typ_max_flag;
@ -264,6 +264,9 @@ extern void pform_dump(ostream&out, Module*mod);
/* /*
* $Log: pform.h,v $ * $Log: pform.h,v $
* Revision 1.66 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.65 2003/01/26 21:15:59 steve * Revision 1.65 2003/01/26 21:15:59 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

7
t-dll-expr.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll-expr.cc,v 1.31 2003/01/27 00:14:37 steve Exp $" #ident "$Id: t-dll-expr.cc,v 1.32 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -34,7 +34,7 @@
/* /*
* This is a little convenience function for converting a NetExpr * This is a little convenience function for converting a NetExpr
* expresion type to the expression type used by ivl_expr_t objects. * expression type to the expression type used by ivl_expr_t objects.
*/ */
static ivl_variable_type_t get_expr_type(const NetExpr*net) static ivl_variable_type_t get_expr_type(const NetExpr*net)
{ {
@ -561,6 +561,9 @@ void dll_target::expr_variable(const NetEVariable*net)
/* /*
* $Log: t-dll-expr.cc,v $ * $Log: t-dll-expr.cc,v $
* Revision 1.32 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.31 2003/01/27 00:14:37 steve * Revision 1.31 2003/01/27 00:14:37 steve
* Support in various contexts the $realtime * Support in various contexts the $realtime
* system task. * system task.

7
t-dll-proc.cc
View File

@ -18,7 +18,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll-proc.cc,v 1.55 2003/01/26 21:15:59 steve Exp $" #ident "$Id: t-dll-proc.cc,v 1.56 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -597,7 +597,7 @@ bool dll_target::proc_release(const NetRelease*net)
stmt_cur_->type_ = IVL_ST_RELEASE; stmt_cur_->type_ = IVL_ST_RELEASE;
/* If there is no signal attached to the release, then it is /* If there is no signal attached to the release, then it is
the victom of an elided net. In that case, simply state the victim of an elided net. In that case, simply state
that there are no lvals, and that's all. */ that there are no lvals, and that's all. */
const NetNet*lsig = net->lval(); const NetNet*lsig = net->lval();
if (lsig == 0) { if (lsig == 0) {
@ -827,6 +827,9 @@ void dll_target::proc_while(const NetWhile*net)
/* /*
* $Log: t-dll-proc.cc,v $ * $Log: t-dll-proc.cc,v $
* Revision 1.56 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.55 2003/01/26 21:15:59 steve * Revision 1.55 2003/01/26 21:15:59 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

7
t-dll.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll.cc,v 1.103 2003/01/26 21:15:59 steve Exp $" #ident "$Id: t-dll.cc,v 1.104 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -1898,7 +1898,7 @@ void dll_target::signal(const NetNet*net)
} }
#endif #endif
/* Save the privitive properties of the signal in the /* Save the primitive properties of the signal in the
ivl_signal_t object. */ ivl_signal_t object. */
obj->width_ = net->pin_count(); obj->width_ = net->pin_count();
@ -2033,6 +2033,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
/* /*
* $Log: t-dll.cc,v $ * $Log: t-dll.cc,v $
* Revision 1.104 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.103 2003/01/26 21:15:59 steve * Revision 1.103 2003/01/26 21:15:59 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

2
t-dll.txt
View File

@ -50,7 +50,7 @@ documentation in the ivl_target.h header file.
* IVL_EX_NUMBER * IVL_EX_NUMBER
This is a constant number. The width is fully known, and the bit This is a constant number. The width is fully known, and the bit
values are all represented by the ascii characters 0, 1, x or z. The values are all represented by the ASCII characters 0, 1, x or z. The
ivl_expr_bits method returns a pointer to the least significant bit, ivl_expr_bits method returns a pointer to the least significant bit,
and the remaining bits are ordered from least significant to most and the remaining bits are ordered from least significant to most
significant. For example, 5'b1zzx0 is the 5 character string "0xzz1". significant. For example, 5'b1zzx0 is the 5 character string "0xzz1".

9
t-xnf.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-xnf.cc,v 1.46 2003/01/14 21:16:18 steve Exp $" #ident "$Id: t-xnf.cc,v 1.47 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -29,7 +29,7 @@
* use by Xilinx tools, and other tools that accepts Xilinx designs. * use by Xilinx tools, and other tools that accepts Xilinx designs.
* *
* The code generator automatically detects ports to top level modules * The code generator automatically detects ports to top level modules
* and generates SIG records that make the XNF useable as a schematic. * and generates SIG records that make the XNF usable as a schematic.
* *
* FLAGS * FLAGS
* The XNF backend uses the following flags from the command line to * The XNF backend uses the following flags from the command line to
@ -61,7 +61,7 @@
* Specify the LCA library part type for the gate. The lname * Specify the LCA library part type for the gate. The lname
* is the name of the symbol to use (i.e. DFF) and the comma * is the name of the symbol to use (i.e. DFF) and the comma
* separated list is the names of the pins, in the order they * separated list is the names of the pins, in the order they
* appear in the verilog source. If the name is prefixed with a * appear in the Verilog source. If the name is prefixed with a
* tilde (~) then the pin is inverted, and the proper "INV" token * tilde (~) then the pin is inverted, and the proper "INV" token
* will be added to the PIN record. * will be added to the PIN record.
* *
@ -927,6 +927,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
/* /*
* $Log: t-xnf.cc,v $ * $Log: t-xnf.cc,v $
* Revision 1.47 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.46 2003/01/14 21:16:18 steve * Revision 1.46 2003/01/14 21:16:18 steve
* Move strstream to ostringstream for compatibility. * Move strstream to ostringstream for compatibility.
* *

9
target.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: target.cc,v 1.64 2003/01/26 21:15:59 steve Exp $" #ident "$Id: target.cc,v 1.65 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -146,7 +146,7 @@ bool target_t::net_cassign(const NetCAssign*dev)
{ {
cerr << "target (" << typeid(*this).name() << "): "; cerr << "target (" << typeid(*this).name() << "): ";
cerr << dev->get_line(); cerr << dev->get_line();
cerr << ": Target does not support procedural continous assignment." << endl; cerr << ": Target does not support procedural continuous assignment." << endl;
return false; return false;
} }
@ -213,7 +213,7 @@ bool target_t::proc_cassign(const NetCAssign*dev)
{ {
cerr << "target (" << typeid(*this).name() << "): "; cerr << "target (" << typeid(*this).name() << "): ";
cerr << dev->get_line(); cerr << dev->get_line();
cerr << ": Target does not support procedural continous assignment." << endl; cerr << ": Target does not support procedural continuous assignment." << endl;
return false; return false;
} }
@ -403,6 +403,9 @@ void expr_scan_t::expr_binary(const NetEBinary*ex)
/* /*
* $Log: target.cc,v $ * $Log: target.cc,v $
* Revision 1.65 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.64 2003/01/26 21:15:59 steve * Revision 1.64 2003/01/26 21:15:59 steve
* Rework expression parsing and elaboration to * Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions. * accommodate real/realtime values and expressions.

9
verinum.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: verinum.cc,v 1.35 2002/08/19 02:39:17 steve Exp $" #ident "$Id: verinum.cc,v 1.36 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -201,7 +201,7 @@ unsigned long verinum::as_ulong() const
* *
* This function presumes that the native format is 2s compliment * This function presumes that the native format is 2s compliment
* (pretty safe these days) and masks/sets bits accordingly. If the * (pretty safe these days) and masks/sets bits accordingly. If the
* value is too large for the lative form, it truncates the high bits. * value is too large for the native form, it truncates the high bits.
*/ */
signed long verinum::as_long() const signed long verinum::as_long() const
{ {
@ -626,7 +626,7 @@ verinum operator - (const verinum&left, const verinum&r)
* result. The resulting number is as large as the sum of the sizes of * result. The resulting number is as large as the sum of the sizes of
* the operand. * the operand.
* *
* The algorithm used is sucessive shift and add operations, * The algorithm used is successive shift and add operations,
* implemented as the nested loops. * implemented as the nested loops.
* *
* If either value is not completely defined, then the result is not * If either value is not completely defined, then the result is not
@ -815,6 +815,9 @@ verinum::V operator & (verinum::V l, verinum::V r)
/* /*
* $Log: verinum.cc,v $ * $Log: verinum.cc,v $
* Revision 1.36 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.35 2002/08/19 02:39:17 steve * Revision 1.35 2002/08/19 02:39:17 steve
* Support parameters with defined ranges. * Support parameters with defined ranges.
* *

9
verinum.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: verinum.h,v 1.21 2003/01/30 04:23:25 steve Exp $" #ident "$Id: verinum.h,v 1.22 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include <string> # include <string>
@ -32,7 +32,7 @@ class ostream;
#endif #endif
/* /*
* Numbers in verlog are multibit strings, where each bit has 4 * Numbers in Verilog are multibit strings, where each bit has 4
* possible values: 0, 1, x or z. The verinum number is store in * possible values: 0, 1, x or z. The verinum number is store in
* little-endian format. This means that if the long value is 2b'10, * little-endian format. This means that if the long value is 2b'10,
* get(0) is 0 and get(1) is 1. * get(0) is 0 and get(1) is 1.
@ -73,7 +73,7 @@ class verinum {
bool is_defined() const; bool is_defined() const;
// A number is "a string" if its value came directly from // A number is "a string" if its value came directly from
// an ascii description instead of a number value. // an ASCII description instead of a number value.
bool is_string() const { return string_flag_; } bool is_string() const { return string_flag_; }
// Comparison for use in sorting algorithms. // Comparison for use in sorting algorithms.
@ -131,6 +131,9 @@ extern verinum v_not(const verinum&left);
/* /*
* $Log: verinum.h,v $ * $Log: verinum.h,v $
* Revision 1.22 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.21 2003/01/30 04:23:25 steve * Revision 1.21 2003/01/30 04:23:25 steve
* include config.h to get iosfwd flags. * include config.h to get iosfwd flags.
* *

2
xilinx-hint.txt
View File

@ -77,7 +77,7 @@ xnf2pcf <$2.xnf >! $2.pcf
There is now a "Xilinx on Linux HOWTO" at There is now a "Xilinx on Linux HOWTO" at
http://www.polybus.com/xilinx_on_linux.html http://www.polybus.com/xilinx_on_linux.html
I havn't tried this yet, it looks interesting. I haven't tried this yet, it looks interesting.
Downloading: Downloading:

13
xnf.txt
View File

@ -86,7 +86,7 @@ an I/OBUF by attaching an attribute to the device, like so:
buf b1 (sig, foo); buf b1 (sig, foo);
$attribute(b1, "XNF-LCA", "OBUF:O,I"); $attribute(b1, "XNF-LCA", "OBUF:O,I");
This latter feature is not entirely recomended as it expects that the This latter feature is not entirely recommended as it expects that the
programmer really knows how the pins of the XNF device are to be programmer really knows how the pins of the XNF device are to be
connected. It also bypasses the efforts of the compiler, so is not connected. It also bypasses the efforts of the compiler, so is not
checked for correctness. checked for correctness.
@ -94,7 +94,7 @@ checked for correctness.
XNF STORAGE ELEMENTS XNF STORAGE ELEMENTS
Storage elements in XNF include flip-flops, latches and CLB Storage elements in XNF include flip-flops, latches and CLB
rams. These devices are generated from the LPM equivilents that the rams. These devices are generated from the LPM equivalents that the
-Fsynth functor synthesizes from behavioral descriptions. -Fsynth functor synthesizes from behavioral descriptions.
Flip-flops, or more specifically DFF devices, are generated to Flip-flops, or more specifically DFF devices, are generated to
@ -104,14 +104,14 @@ implement behavioral code like this:
always @(posedge clk) Q <= <expr>; always @(posedge clk) Q <= <expr>;
The edge can be positive or negative, and the expression can be any The edge can be positive or negative, and the expression can be any
synthesizeable expression. Furthermore, the register "Q" can have synthesizable expression. Furthermore, the register "Q" can have
width, which will cause the appropriate number of flip-flops to be width, which will cause the appropriate number of flip-flops to be
created. A clock enable expression can also be added like so: created. A clock enable expression can also be added like so:
reg Q; reg Q;
always @(posedge clk) if (<ce>) Q <= <expr>; always @(posedge clk) if (<ce>) Q <= <expr>;
The <ce> expression can be any synthesizeable expression. The <ce> expression can be any synthesizable expression.
With or without the CE, the generated DFF devices are written into the With or without the CE, the generated DFF devices are written into the
XNF output one bit at a time, with the clock input inverted if necessary. XNF output one bit at a time, with the clock input inverted if necessary.
@ -130,7 +130,7 @@ device can be modeled with ordinary structural code, i.e.:
assign foo <= M[<addr>]; assign foo <= M[<addr>];
For the memory to be synthesizeable in the XNF target, the address For the memory to be synthesizable in the XNF target, the address
lines for writes and reads must be connected. This corresponds to the lines for writes and reads must be connected. This corresponds to the
limitations of the real hardware. limitations of the real hardware.
@ -245,6 +245,9 @@ IBUF, NOT gates cannot be absorbed as in the OPAD case.
$Log: xnf.txt,v $ $Log: xnf.txt,v $
Revision 1.15 2003/01/30 16:23:08 steve
Spelling fixes.
Revision 1.14 2000/08/01 21:32:40 steve Revision 1.14 2000/08/01 21:32:40 steve
Use the iverilog command in documentation. Use the iverilog command in documentation.

7
xnfio.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: xnfio.cc,v 1.24 2003/01/14 21:16:18 steve Exp $" #ident "$Id: xnfio.cc,v 1.25 2003/01/30 16:23:08 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -227,7 +227,7 @@ static void make_ibuf(Design*des, NetNet*net)
if (tmp->attribute("XNF-LCA") != verinum()) if (tmp->attribute("XNF-LCA") != verinum())
continue; continue;
// Found a BUF, it is only useable if the only input is // Found a BUF, it is only usable if the only input is
// the signal and there are no other inputs. // the signal and there are no other inputs.
if ((tmp->type() == NetLogic::BUF) && if ((tmp->type() == NetLogic::BUF) &&
(count_inputs(tmp->pin(1)) == 1) && (count_inputs(tmp->pin(1)) == 1) &&
@ -362,6 +362,9 @@ void xnfio(Design*des)
/* /*
* $Log: xnfio.cc,v $ * $Log: xnfio.cc,v $
* Revision 1.25 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.24 2003/01/14 21:16:18 steve * Revision 1.24 2003/01/14 21:16:18 steve
* Move strstream to ostringstream for compatibility. * Move strstream to ostringstream for compatibility.
* *