Add the glossary file.

driver/iverilog.man

@@ -1,4 +1,4 @@
-.TH iverilog 1 "$Date: 2001/01/20 19:02:05 $" Version "$Date: 2001/01/20 19:02:05 $"
+.TH iverilog 1 "$Date: 2001/05/15 15:09:08 $" Version "$Date: 2001/05/15 15:09:08 $"
 .SH NAME
 iverilog - Icarus Verilog compiler
 
@@ -10,9 +10,10 @@ iverilog - Icarus Verilog compiler
 .PP
 \fIiverilog\fP is a compiler that translates Verilog source code into
 executable programs for simulation, or other netlist formats for
-further processing. The currenty supported targets are \fIvvm\fP (for
+further processing. The currently supported targets are \fIvvm\fP (for
-executable simulation) and \fIxnf\fP for synthesis. Other target
+executable simulation) and \fIvvp\fP for simulation, and \fIxnf\fP for
-types are added as code generators are implemented.
+synthesis. Other target types are added as code generators are
+implemented.
 
 .SH OPTIONS
 .l
@@ -56,7 +57,7 @@ expanded and removed. This is useful, for example, to preprocess
 verilog source for use by other compilers.
 .TP 8
 .B -I\fIincludedir\fP 
-Append directory \fIincludepdir\fP to list of directoriess searched
+Append directory \fIincludepdir\fP to list of directories searched
 for Verilog include files. The \fB-I\fP switch may be used many times
 to specify several directories to search, the directories are searched
 in the order they appear on the command line.
@@ -64,7 +65,7 @@ in the order they appear on the command line.
 .B -m\fImodule\fP
 Add this module to the list of VPI modules to be loaded by the
 simulation. Many modules can be specified, and all will be loaded, in
-the order specified.
+the order specified. The system module is implicit and always included.
 .TP 8
 .B -N\fIpath\fP
 This is used for debugging the compiler proper. Dump the final netlist
@@ -133,6 +134,12 @@ This is the default. The target is an executable program that uses the
 vvm simulation runtime. The compiler actually generates C++ code, then
 compiles and links that code to make the output executable.
 .TP 8
+.B vvp
+The vvp target generates code for the vvp runtime. The output is a
+complete program that simulates the design (like with vvm) but must be
+run by the \fivvp\fP command. This target is much faster then the
+\fBvvm\fP target, but not quite as complete.
+.TP 8
 .B xnf
 This is the Xilinx Netlist Format used by many tools for placing
 devices in FPGAs or other programmable devices. The Icarus Verilog XNF
@@ -159,15 +166,19 @@ the current directory
 
 To compile hello.v to an executable file called a.out:
 
-	verilog hello.v
+	iverilog hello.v
 
 To compile hello.v to an executable file called hello:
 
-	verilog -o hello hello.v
+	iverilog -o hello hello.v
+
+To compile and run using the vvp runtime:
+
+	iverilog -ohello.vvp -tvvp hello.v
 
 To compile hello.v to a file in XNF-format called hello.xnf
 
-	verilog -txnf -ohello.xnf hello.v
+	iverilog -txnf -ohello.xnf hello.v
 
 
 .SH "AUTHOR"

glossary.txt

@@ -0,0 +1,39 @@
+
+Throughout Icarus Verilog descriptions and source code, I use a
+variety of terms and acronyms that might be specific to Icarus
+Verilog, have an Icarus Verilog specific meaning, or just aren't
+widely known. So here I define these terms.
+
+
+LRM     - Language Reference Manual
+    This is a generic acronym, but in the Verilog world we sometimes
+    mean *the* language reference manual, the IEEE1364 standard.
+
+
+PLI     - Programming Language Interface
+    This is a C API into Verilog simulators that is defined by the
+    IEEE1364. There are two major interfaces, sometimes called PLI 1
+    and PLI 2. PLI 2 is also often called VPI.
+
+
+UDP     - User Defined Primitive
+    These are objects that Verilog programmers define with the
+    "primitive" keyword. They are truth-table based devices. The
+    syntax for defining them is described in the LRM.
+
+
+VPI     -
+    This is the C API that is defined by the Verilog standard, and
+    that Icarus Verilog partially implements. See also PLI.
+
+
+VVM     - Verilog Virtual Machine
+    This is the Icarus Verilog runtime that works with the code
+    generator that generates C++.
+
+
+VVP     - Verilog Virtual Processor
+    This is the Icarus Verilog runtime that reads in custom code in a
+    form that I call "VVP Assembly". See the vvp/ directory for
+    documentation on that.
+

vvp/vpi_signal.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: vpi_signal.cc,v 1.12 2001/05/14 00:42:32 steve Exp $"
+#ident "$Id: vpi_signal.cc,v 1.13 2001/05/15 15:09:08 steve Exp $"
 #endif
 
 /*
@@ -170,6 +170,25 @@ static void signal_get_value(vpiHandle ref, s_vpi_value*vp)
 
       switch (vp->format) {
 
+	  case vpiIntVal:
+	    assert(wid <= 8 * sizeof vp->value.integer);
+	    vp->value.integer = 0;
+	    for (unsigned idx = 0 ;  idx < wid ;  idx += 1) {
+		  vvp_ipoint_t fptr = ipoint_index(rfp->bits, idx);
+		  switch (functor_oval(fptr)) {
+		      case 0:
+			break;
+		      case 1:
+			vp->value.integer |= 1<<idx;
+			break;
+		      default:
+			idx = wid;
+			vp->value.integer = 0;
+			break;
+		  }
+	    }
+	    break;
+
 	  case vpiBinStrVal:
 	    for (unsigned idx = 0 ;  idx < wid ;  idx += 1) {
 		  vvp_ipoint_t fptr = ipoint_index(rfp->bits, idx);
@@ -407,6 +426,9 @@ vpiHandle vpip_make_net(char*name, int msb, int lsb, bool signed_flag,
 
 /*
  * $Log: vpi_signal.cc,v $
+ * Revision 1.13  2001/05/15 15:09:08  steve
+ *  Add the glossary file.
+ *
  * Revision 1.12  2001/05/14 00:42:32  steve
  *  test width of target with bit size of long.
  *