Add synthesis support for synchronous reset.
This commit is contained in:
steve
parent
855c2fe001
commit
e561819179
3
ivl.def
3
ivl.def
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@ -78,6 +78,9 @@ ivl_lpm_select
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ivl_lpm_selects
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ivl_lpm_signed
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ivl_lpm_size
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ivl_lpm_sset_value
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ivl_lpm_sync_clr
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ivl_lpm_sync_set
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ivl_lpm_type
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ivl_lpm_width
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: ivl_target.h,v 1.120 2003/07/30 01:13:28 steve Exp $"
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#ident "$Id: ivl_target.h,v 1.121 2003/08/15 02:23:52 steve Exp $"
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#endif
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#ifdef __cplusplus
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@ -668,6 +668,9 @@ extern unsigned ivl_lpm_width(ivl_lpm_t net);
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extern ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net);
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extern ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net);
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extern ivl_expr_t ivl_lpm_aset_value(ivl_lpm_t net);
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extern ivl_nexus_t ivl_lpm_sync_clr(ivl_lpm_t net);
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extern ivl_nexus_t ivl_lpm_sync_set(ivl_lpm_t net);
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extern ivl_expr_t ivl_lpm_sset_value(ivl_lpm_t net);
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/* IVL_LPM_FF IVL_LPM_RAM */
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extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
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/* IVL_LPM_UFUNC */
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@ -1220,6 +1223,9 @@ _END_DECL
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/*
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* $Log: ivl_target.h,v $
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* Revision 1.121 2003/08/15 02:23:52 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.120 2003/07/30 01:13:28 steve
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* Add support for triand and trior.
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*
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20
netlist.cc
20
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.cc,v 1.217 2003/07/05 20:42:08 steve Exp $"
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#ident "$Id: netlist.cc,v 1.218 2003/08/15 02:23:52 steve Exp $"
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#endif
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# include "config.h"
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@ -622,6 +622,11 @@ Link& NetFF::pin_Sclr()
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return pin(7);
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}
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const Link& NetFF::pin_Sclr() const
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{
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return pin(7);
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}
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Link& NetFF::pin_Data(unsigned w)
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{
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unsigned pn = 8 + 2*w;
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@ -660,6 +665,16 @@ const verinum& NetFF::aset_value() const
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return aset_value_;
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}
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void NetFF::sset_value(const verinum&val)
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{
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sset_value_ = val;
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}
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const verinum& NetFF::sset_value() const
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{
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return sset_value_;
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}
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/*
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* The NetAddSub class represents an LPM_ADD_SUB device. The pinout is
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@ -2179,6 +2194,9 @@ const NetProc*NetTaskDef::proc() const
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/*
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* $Log: netlist.cc,v $
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* Revision 1.218 2003/08/15 02:23:52 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.217 2003/07/05 20:42:08 steve
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* Fix some enumeration warnings.
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*
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11
netlist.h
11
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.h,v 1.296 2003/08/09 03:23:40 steve Exp $"
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#ident "$Id: netlist.h,v 1.297 2003/08/15 02:23:52 steve Exp $"
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#endif
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/*
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@ -680,18 +680,24 @@ class NetFF : public NetNode {
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const Link& pin_Enable() const;
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const Link& pin_Aset() const;
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const Link& pin_Aclr() const;
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const Link& pin_Sset() const;
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const Link& pin_Sclr() const;
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const Link& pin_Data(unsigned) const;
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const Link& pin_Q(unsigned) const;
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void aset_value(const verinum&val);
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const verinum& aset_value() const;
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void sset_value(const verinum&val);
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const verinum& sset_value() const;
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virtual void dump_node(ostream&, unsigned ind) const;
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virtual bool emit_node(struct target_t*) const;
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virtual void functor_node(Design*des, functor_t*fun);
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private:
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verinum aset_value_;
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verinum sset_value_;
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};
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@ -3316,6 +3322,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.297 2003/08/15 02:23:52 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.296 2003/08/09 03:23:40 steve
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* Add support for IVL_LPM_MULT device.
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*
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71
synth2.cc
71
synth2.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2002-2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.29 2003/08/14 02:41:05 steve Exp $"
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#ident "$Id: synth2.cc,v 1.30 2003/08/15 02:23:53 steve Exp $"
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#endif
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# include "config.h"
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@ -387,6 +387,7 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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tmp_map->pin_count());
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verinum tmp_aset = ff->aset_value();
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verinum tmp_sset = ff->sset_value();
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/* Create a new DFF to handle this part of the begin-end
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block. Connect this NetFF to the associated pins of
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@ -397,15 +398,23 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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des->add_node(ff2);
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verinum aset_value2 (verinum::V1, ff2->width());
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verinum sset_value2 (verinum::V1, ff2->width());
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for (unsigned idx = 0 ; idx < ff2->width() ; idx += 1) {
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unsigned ptr = find_nexus_in_set(nex_map,
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tmp_map->pin(idx).nexus());
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/* Connect Data and Q bits to the new FF. */
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connect(ff->pin_Data(ptr), ff2->pin_Data(idx));
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connect(ff->pin_Q(ptr), ff2->pin_Q(idx));
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/* Copy the asynch set bit to the new device. */
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if (ptr < tmp_aset.len())
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aset_value2.set(idx, tmp_aset[ptr]);
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/* Copy the synch set bit to the new device. */
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if (ptr < tmp_sset.len())
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sset_value2.set(idx, tmp_sset[ptr]);
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if (pin_accounting[ptr] != 0) {
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cerr << cur->get_line() << ": error: "
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<< "Synchronous output conflicts with "
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@ -417,10 +426,15 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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pin_accounting[ptr] = cur;
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}
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}
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if (ff->pin_Aclr().is_linked())
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connect(ff->pin_Aclr(), ff2->pin_Aclr());
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if (ff->pin_Aset().is_linked())
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connect(ff->pin_Aset(), ff2->pin_Aset());
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if (ff->pin_Sclr().is_linked())
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connect(ff->pin_Sclr(), ff2->pin_Sclr());
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if (ff->pin_Sset().is_linked())
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connect(ff->pin_Sset(), ff2->pin_Sset());
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if (ff->pin_Clock().is_linked())
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connect(ff->pin_Clock(), ff2->pin_Clock());
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if (ff->pin_Enable().is_linked())
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@ -560,6 +574,56 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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delete expr_input;
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/* Detect the case that this is a *synchronous* set/reset. It
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is not asyncronous because we know the condition is not
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included in the sensitivity list, but if the if_ case is
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constant (has no inputs) then we can model this as a
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synchronous set/reset. */
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NexusSet*a_set = if_->nex_input();
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if (a_set->count() == 0) {
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NetNet*rst = expr_->synthesize(des);
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assert(rst->pin_count() == 1);
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/* Synthesize the true clause to figure out what
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kind of set/reset we have. */
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NetNet*asig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, nex_map->pin_count());
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asig->local_flag(true);
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bool flag = if_->synth_async(des, scope, nex_map, asig);
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assert(asig->pin_count() == ff->width());
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/* Collect the set/reset value into a verinum. If
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this turns out to be entirely 0 values, then
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use the Sclr input. Otherwise, use the Aset
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input and save the set value. */
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verinum tmp (verinum::V0, ff->width());
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for (unsigned bit = 0 ; bit < ff->width() ; bit += 1) {
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assert(asig->pin(bit).nexus()->drivers_constant());
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tmp.set(bit, asig->pin(bit).nexus()->driven_value());
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}
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assert(tmp.is_defined());
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if (tmp.is_zero()) {
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connect(ff->pin_Sclr(), rst->pin(0));
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} else {
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connect(ff->pin_Sset(), rst->pin(0));
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ff->sset_value(tmp);
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}
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delete a_set;
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return else_->synth_sync(des, scope, ff, nex_map,
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nex_out, svector<NetEvProbe*>(0))
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&& flag;
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}
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delete a_set;
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/* Failed to find an asynchronous set/reset, so any events
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input are probably in error. */
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if (events_in.count() > 0) {
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@ -813,6 +877,9 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.30 2003/08/15 02:23:53 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.29 2003/08/14 02:41:05 steve
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* Fix dangling pointer in NexusSet handling blocks.
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*
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29
t-dll-api.cc
29
t-dll-api.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll-api.cc,v 1.101 2003/06/24 01:38:03 steve Exp $"
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#ident "$Id: t-dll-api.cc,v 1.102 2003/08/15 02:23:53 steve Exp $"
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#endif
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# include "config.h"
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@ -620,6 +620,18 @@ extern "C" ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net)
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}
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}
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extern "C" ivl_nexus_t ivl_lpm_sync_clr(ivl_lpm_t net)
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{
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assert(net);
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switch(net->type) {
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case IVL_LPM_FF:
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return net->u_.ff.sclr;
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default:
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assert(0);
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return 0;
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}
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}
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extern "C" ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net)
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{
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assert(net);
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@ -632,6 +644,18 @@ extern "C" ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net)
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}
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}
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extern "C" ivl_nexus_t ivl_lpm_sync_set(ivl_lpm_t net)
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{
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assert(net);
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switch(net->type) {
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case IVL_LPM_FF:
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return net->u_.ff.sset;
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default:
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assert(0);
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return 0;
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}
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}
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extern "C" ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net)
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{
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assert(net);
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@ -1848,6 +1872,9 @@ extern "C" ivl_variable_type_t ivl_variable_type(ivl_variable_t net)
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/*
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* $Log: t-dll-api.cc,v $
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* Revision 1.102 2003/08/15 02:23:53 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.101 2003/06/24 01:38:03 steve
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* Various warnings fixed.
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*
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15
t-dll.cc
15
t-dll.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll.cc,v 1.118 2003/07/30 01:13:28 steve Exp $"
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#ident "$Id: t-dll.cc,v 1.119 2003/08/15 02:23:53 steve Exp $"
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#endif
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# include "config.h"
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@ -1527,6 +1527,16 @@ void dll_target::lpm_ff(const NetFF*net)
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obj->u_.ff.aset_value = 0;
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}
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if (net->pin_Sclr().is_linked()) {
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nex = net->pin_Sclr().nexus();
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assert(nex->t_cookie());
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obj->u_.ff.sclr = (ivl_nexus_t) nex->t_cookie();
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assert(obj->u_.ff.sclr);
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nexus_lpm_add(obj->u_.ff.sclr, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
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} else {
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obj->u_.ff.sclr = 0;
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}
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if (obj->u_.ff.width == 1) {
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nex = net->pin_Q(0).nexus();
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assert(nex->t_cookie());
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@ -2134,6 +2144,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
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/*
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* $Log: t-dll.cc,v $
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* Revision 1.119 2003/08/15 02:23:53 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.118 2003/07/30 01:13:28 steve
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* Add support for triand and trior.
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*
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67
t-dll.h
67
t-dll.h
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@ -1,7 +1,7 @@
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#ifndef __t_dll_H
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#define __t_dll_H
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/*
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* Copyright (c) 2000-2002 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll.h,v 1.104 2003/06/23 01:25:44 steve Exp $"
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#ident "$Id: t-dll.h,v 1.105 2003/08/15 02:23:53 steve Exp $"
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#endif
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# include "target.h"
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@ -299,6 +299,8 @@ struct ivl_lpm_s {
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ivl_nexus_t we;
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ivl_nexus_t aclr;
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ivl_nexus_t aset;
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ivl_nexus_t sclr;
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ivl_nexus_t sset;
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union {
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ivl_nexus_t*pins;
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ivl_nexus_t pin;
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@ -681,6 +683,9 @@ struct ivl_variable_s {
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/*
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* $Log: t-dll.h,v $
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* Revision 1.105 2003/08/15 02:23:53 steve
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* Add synthesis support for synchronous reset.
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*
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* Revision 1.104 2003/06/23 01:25:44 steve
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* Module attributes make it al the way to ivl_target.
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*
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@ -723,63 +728,5 @@ struct ivl_variable_s {
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*
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* Revision 1.94 2002/09/26 03:18:04 steve
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* Generate vvp code for asynch set/reset of NetFF.
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*
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* Revision 1.93 2002/08/12 01:35:01 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.92 2002/08/07 02:36:10 steve
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* Get local StringHeap.h
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*
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* Revision 1.91 2002/08/07 00:54:39 steve
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* Add force to nets.
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*
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* Revision 1.90 2002/08/05 04:18:45 steve
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* Store only the base name of memories.
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*
|
||||
* Revision 1.89 2002/08/04 19:13:16 steve
|
||||
* dll uses StringHeap for named items.
|
||||
*
|
||||
* Revision 1.88 2002/08/04 18:28:15 steve
|
||||
* Do not use hierarchical names of memories to
|
||||
* generate vvp labels. -tdll target does not
|
||||
* used hierarchical name string to look up the
|
||||
* memory objects in the design.
|
||||
*
|
||||
* Revision 1.87 2002/07/05 21:26:17 steve
|
||||
* Avoid emitting to vvp local net symbols.
|
||||
*
|
||||
* Revision 1.86 2002/06/21 04:59:35 steve
|
||||
* Carry integerness throughout the compilation.
|
||||
*
|
||||
* Revision 1.85 2002/06/16 20:39:12 steve
|
||||
* Normalize run-time index expressions for bit selects
|
||||
*
|
||||
* Revision 1.84 2002/06/16 19:19:16 steve
|
||||
* Generate runtime code to normalize indices.
|
||||
*
|
||||
* Revision 1.83 2002/06/05 03:44:25 steve
|
||||
* Add support for memory words in l-value of
|
||||
* non-blocking assignments, and remove the special
|
||||
* NetAssignMem_ and NetAssignMemNB classes.
|
||||
*
|
||||
* Revision 1.82 2002/06/04 05:38:44 steve
|
||||
* Add support for memory words in l-value of
|
||||
* blocking assignments, and remove the special
|
||||
* NetAssignMem class.
|
||||
*
|
||||
* Revision 1.81 2002/05/29 22:05:55 steve
|
||||
* Offset lvalue index expressions.
|
||||
*
|
||||
* Revision 1.80 2002/05/27 00:08:45 steve
|
||||
* Support carrying the scope of named begin-end
|
||||
* blocks down to the code generator, and have
|
||||
* the vvp code generator use that to support disable.
|
||||
*
|
||||
* Revision 1.79 2002/05/26 01:39:03 steve
|
||||
* Carry Verilog 2001 attributes with processes,
|
||||
* all the way through to the ivl_target API.
|
||||
*
|
||||
* Divide signal reference counts between rval
|
||||
* and lval references.
|
||||
*/
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: d-lpm.c,v 1.5 2003/08/10 16:42:23 steve Exp $"
|
||||
#ident "$Id: d-lpm.c,v 1.6 2003/08/15 02:23:53 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -350,9 +350,10 @@ static void lpm_show_dff(ivl_lpm_t net)
|
|||
unsigned idx;
|
||||
unsigned pin, wid = ivl_lpm_width(net);
|
||||
|
||||
sprintf(name, "fd%s%s%u",
|
||||
sprintf(name, "fd%s%s%s%u",
|
||||
ivl_lpm_enable(net)? "ce" : "",
|
||||
ivl_lpm_async_clr(net)? "cl" : "",
|
||||
ivl_lpm_sync_clr(net)? "sc" : "",
|
||||
wid);
|
||||
|
||||
cell = edif_xlibrary_findcell(xlib, name);
|
||||
|
|
@ -364,6 +365,8 @@ static void lpm_show_dff(ivl_lpm_t net)
|
|||
nports += 1;
|
||||
if (ivl_lpm_async_clr(net))
|
||||
nports += 1;
|
||||
if (ivl_lpm_sync_clr(net))
|
||||
nports += 1;
|
||||
|
||||
cell = edif_xcell_create(xlib, strdup(name), nports);
|
||||
edif_cell_pstring(cell, "LPM_Type", "LPM_FF");
|
||||
|
|
@ -392,6 +395,11 @@ static void lpm_show_dff(ivl_lpm_t net)
|
|||
pin += 1;
|
||||
}
|
||||
|
||||
if (ivl_lpm_sync_clr(net)) {
|
||||
edif_cell_portconfig(cell, pin, "Sclr", IVL_SIP_INPUT);
|
||||
pin += 1;
|
||||
}
|
||||
|
||||
edif_cell_portconfig(cell, pin, "Clock", IVL_SIP_INPUT);
|
||||
pin += 1;
|
||||
|
||||
|
|
@ -419,6 +427,13 @@ static void lpm_show_dff(ivl_lpm_t net)
|
|||
edif_add_to_joint(jnt, ref, pin);
|
||||
}
|
||||
|
||||
if (ivl_lpm_sync_clr(net)) {
|
||||
pin = edif_cell_port_byname(cell, "Sclr");
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_sync_clr(net));
|
||||
edif_add_to_joint(jnt, ref, pin);
|
||||
}
|
||||
|
||||
for (idx = 0 ; idx < wid ; idx += 1) {
|
||||
|
||||
sprintf(name, "Q%u", idx);
|
||||
|
|
@ -690,6 +705,9 @@ const struct device_s d_lpm_edif = {
|
|||
|
||||
/*
|
||||
* $Log: d-lpm.c,v $
|
||||
* Revision 1.6 2003/08/15 02:23:53 steve
|
||||
* Add synthesis support for synchronous reset.
|
||||
*
|
||||
* Revision 1.5 2003/08/10 16:42:23 steve
|
||||
* Add async clear to LPM_FF devices.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: d-virtex.c,v 1.31 2003/07/04 00:10:09 steve Exp $"
|
||||
#ident "$Id: d-virtex.c,v 1.32 2003/08/15 02:23:53 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "device.h"
|
||||
|
|
@ -249,6 +249,8 @@ void virtex_generic_dff(ivl_lpm_t net)
|
|||
|
||||
ivl_nexus_t aclr = ivl_lpm_async_clr(net);
|
||||
ivl_nexus_t aset = ivl_lpm_async_set(net);
|
||||
ivl_nexus_t sclr = ivl_lpm_sync_clr(net);
|
||||
ivl_nexus_t sset = ivl_lpm_sync_set(net);
|
||||
const char*abits = 0;
|
||||
|
||||
if (aset) {
|
||||
|
|
@ -258,6 +260,10 @@ void virtex_generic_dff(ivl_lpm_t net)
|
|||
assert(abits);
|
||||
}
|
||||
|
||||
/* XXXX Can't handle both synchronous and asynchronous clear. */
|
||||
assert( ! (aclr && sclr) );
|
||||
/* XXXX Can't handle synchronous set at all. */
|
||||
assert( ! sset );
|
||||
|
||||
for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
|
||||
edif_cellref_t obj;
|
||||
|
|
@ -268,10 +274,15 @@ void virtex_generic_dff(ivl_lpm_t net)
|
|||
an FDCE device. */
|
||||
if (aset && (abits[idx] == '1')) {
|
||||
obj = edif_cellref_create(edf, xilinx_cell_fdcpe(xlib));
|
||||
} else if (aclr) {
|
||||
obj = edif_cellref_create(edf, xilinx_cell_fdce(xlib));
|
||||
} else if (sclr) {
|
||||
obj = edif_cellref_create(edf, xilinx_cell_fdre(xlib));
|
||||
} else {
|
||||
obj = edif_cellref_create(edf, xilinx_cell_fdce(xlib));
|
||||
}
|
||||
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
|
||||
edif_add_to_joint(jnt, obj, FDCE_Q);
|
||||
|
||||
|
|
@ -289,6 +300,9 @@ void virtex_generic_dff(ivl_lpm_t net)
|
|||
if (aclr) {
|
||||
jnt = edif_joint_of_nexus(edf, aclr);
|
||||
edif_add_to_joint(jnt, obj, FDCE_CLR);
|
||||
} else if (sclr) {
|
||||
jnt = edif_joint_of_nexus(edf, sclr);
|
||||
edif_add_to_joint(jnt, obj, FDCE_CLR);
|
||||
}
|
||||
|
||||
if (aset) {
|
||||
|
|
@ -831,6 +845,9 @@ const struct device_s d_virtex_edif = {
|
|||
|
||||
/*
|
||||
* $Log: d-virtex.c,v $
|
||||
* Revision 1.32 2003/08/15 02:23:53 steve
|
||||
* Add synthesis support for synchronous reset.
|
||||
*
|
||||
* Revision 1.31 2003/07/04 00:10:09 steve
|
||||
* Generate MUXF5 based 4-input N-wide muxes.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: xilinx.c,v 1.9 2003/07/04 01:08:03 steve Exp $"
|
||||
#ident "$Id: xilinx.c,v 1.10 2003/08/15 02:23:53 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "edif.h"
|
||||
|
|
@ -206,6 +206,20 @@ edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib)
|
|||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "FDRE", 5);
|
||||
edif_cell_portconfig(cell, FDCE_Q, "Q", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_D, "D", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, FDCE_C, "C", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_CE, "CE", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_CLR,"R", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
|
||||
edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib)
|
||||
{
|
||||
|
|
@ -937,6 +951,9 @@ void xilinx_shiftl(ivl_lpm_t net)
|
|||
|
||||
/*
|
||||
* $Log: xilinx.c,v $
|
||||
* Revision 1.10 2003/08/15 02:23:53 steve
|
||||
* Add synthesis support for synchronous reset.
|
||||
*
|
||||
* Revision 1.9 2003/07/04 01:08:03 steve
|
||||
* PAD attribute can be used to assign pins.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: xilinx.h,v 1.7 2003/07/04 00:10:09 steve Exp $"
|
||||
#ident "$Id: xilinx.h,v 1.8 2003/08/15 02:23:53 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -67,8 +67,12 @@ extern edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib);
|
|||
|
||||
/* === Flip-Flop Devices === */
|
||||
|
||||
/*
|
||||
* These are flip-flops of various sort, but similar pinouts.
|
||||
*/
|
||||
extern edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib);
|
||||
#define FDCE_Q 0
|
||||
#define FDCE_C 1
|
||||
#define FDCE_D 2
|
||||
|
|
@ -126,6 +130,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
|
|||
|
||||
/*
|
||||
* $Log: xilinx.h,v $
|
||||
* Revision 1.8 2003/08/15 02:23:53 steve
|
||||
* Add synthesis support for synchronous reset.
|
||||
*
|
||||
* Revision 1.7 2003/07/04 00:10:09 steve
|
||||
* Generate MUXF5 based 4-input N-wide muxes.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,10 +1,10 @@
|
|||
Summary: Icarus Verilog
|
||||
Name: verilog
|
||||
Version: 0.7.20030730
|
||||
Version: 0.7.20030810
|
||||
Release: 0
|
||||
Copyright: GPL
|
||||
Group: Applications/Engineering
|
||||
Source: ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20030730.tar.gz
|
||||
Source: ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20030810.tar.gz
|
||||
URL: http://www.icarus.com/eda/verilog/index.html
|
||||
Packager: Stephen Williams <steve@icarus.com>
|
||||
|
||||
|
|
@ -22,7 +22,7 @@ engineering formats, including simulation. It strives to be true
|
|||
to the IEEE-1364 standard.
|
||||
|
||||
%prep
|
||||
%setup -n verilog-20030730
|
||||
%setup -n verilog-20030810
|
||||
|
||||
%build
|
||||
%ifarch x86_64
|
||||
|
|
|
|||
Loading…
Reference in New Issue