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Add synthesis support for synchronous reset.

This commit is contained in:
steve 2003-08-15 02:23:52 +00:00
parent 855c2fe001
commit e561819179
13 changed files with 224 additions and 75 deletions
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3
ivl.def
View File

@ -78,6 +78,9 @@ ivl_lpm_select
ivl_lpm_selects ivl_lpm_selects
ivl_lpm_signed ivl_lpm_signed
ivl_lpm_size ivl_lpm_size
ivl_lpm_sset_value
ivl_lpm_sync_clr
ivl_lpm_sync_set
ivl_lpm_type ivl_lpm_type
ivl_lpm_width ivl_lpm_width

8
ivl_target.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_target.h,v 1.120 2003/07/30 01:13:28 steve Exp $" #ident "$Id: ivl_target.h,v 1.121 2003/08/15 02:23:52 steve Exp $"
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
@ -668,6 +668,9 @@ extern unsigned ivl_lpm_width(ivl_lpm_t net);
extern ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net); extern ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net);
extern ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net); extern ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net);
extern ivl_expr_t ivl_lpm_aset_value(ivl_lpm_t net); extern ivl_expr_t ivl_lpm_aset_value(ivl_lpm_t net);
extern ivl_nexus_t ivl_lpm_sync_clr(ivl_lpm_t net);
extern ivl_nexus_t ivl_lpm_sync_set(ivl_lpm_t net);
extern ivl_expr_t ivl_lpm_sset_value(ivl_lpm_t net);
/* IVL_LPM_FF IVL_LPM_RAM */ /* IVL_LPM_FF IVL_LPM_RAM */
extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net); extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
/* IVL_LPM_UFUNC */ /* IVL_LPM_UFUNC */
@ -1220,6 +1223,9 @@ _END_DECL
/* /*
* $Log: ivl_target.h,v $ * $Log: ivl_target.h,v $
* Revision 1.121 2003/08/15 02:23:52 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.120 2003/07/30 01:13:28 steve * Revision 1.120 2003/07/30 01:13:28 steve
* Add support for triand and trior. * Add support for triand and trior.
* *

20
netlist.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.cc,v 1.217 2003/07/05 20:42:08 steve Exp $" #ident "$Id: netlist.cc,v 1.218 2003/08/15 02:23:52 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -622,6 +622,11 @@ Link& NetFF::pin_Sclr()
return pin(7); return pin(7);
} }
const Link& NetFF::pin_Sclr() const
{
return pin(7);
}
Link& NetFF::pin_Data(unsigned w) Link& NetFF::pin_Data(unsigned w)
{ {
unsigned pn = 8 + 2*w; unsigned pn = 8 + 2*w;
@ -660,6 +665,16 @@ const verinum& NetFF::aset_value() const
return aset_value_; return aset_value_;
} }
void NetFF::sset_value(const verinum&val)
{
sset_value_ = val;
}
const verinum& NetFF::sset_value() const
{
return sset_value_;
}
/* /*
* The NetAddSub class represents an LPM_ADD_SUB device. The pinout is * The NetAddSub class represents an LPM_ADD_SUB device. The pinout is
@ -2179,6 +2194,9 @@ const NetProc*NetTaskDef::proc() const
/* /*
* $Log: netlist.cc,v $ * $Log: netlist.cc,v $
* Revision 1.218 2003/08/15 02:23:52 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.217 2003/07/05 20:42:08 steve * Revision 1.217 2003/07/05 20:42:08 steve
* Fix some enumeration warnings. * Fix some enumeration warnings.
* *

11
netlist.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.h,v 1.296 2003/08/09 03:23:40 steve Exp $" #ident "$Id: netlist.h,v 1.297 2003/08/15 02:23:52 steve Exp $"
#endif #endif
/* /*
@ -680,18 +680,24 @@ class NetFF : public NetNode {
const Link& pin_Enable() const; const Link& pin_Enable() const;
const Link& pin_Aset() const; const Link& pin_Aset() const;
const Link& pin_Aclr() const; const Link& pin_Aclr() const;
const Link& pin_Sset() const;
const Link& pin_Sclr() const;
const Link& pin_Data(unsigned) const; const Link& pin_Data(unsigned) const;
const Link& pin_Q(unsigned) const; const Link& pin_Q(unsigned) const;
void aset_value(const verinum&val); void aset_value(const verinum&val);
const verinum& aset_value() const; const verinum& aset_value() const;
void sset_value(const verinum&val);
const verinum& sset_value() const;
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
virtual bool emit_node(struct target_t*) const; virtual bool emit_node(struct target_t*) const;
virtual void functor_node(Design*des, functor_t*fun); virtual void functor_node(Design*des, functor_t*fun);
private: private:
verinum aset_value_; verinum aset_value_;
verinum sset_value_;
}; };
@ -3316,6 +3322,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/* /*
* $Log: netlist.h,v $ * $Log: netlist.h,v $
* Revision 1.297 2003/08/15 02:23:52 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.296 2003/08/09 03:23:40 steve * Revision 1.296 2003/08/09 03:23:40 steve
* Add support for IVL_LPM_MULT device. * Add support for IVL_LPM_MULT device.
* *

71
synth2.cc
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com) * Copyright (c) 2002-2003 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: synth2.cc,v 1.29 2003/08/14 02:41:05 steve Exp $" #ident "$Id: synth2.cc,v 1.30 2003/08/15 02:23:53 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -387,6 +387,7 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
tmp_map->pin_count()); tmp_map->pin_count());
verinum tmp_aset = ff->aset_value(); verinum tmp_aset = ff->aset_value();
verinum tmp_sset = ff->sset_value();
/* Create a new DFF to handle this part of the begin-end /* Create a new DFF to handle this part of the begin-end
block. Connect this NetFF to the associated pins of block. Connect this NetFF to the associated pins of
@ -397,15 +398,23 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
des->add_node(ff2); des->add_node(ff2);
verinum aset_value2 (verinum::V1, ff2->width()); verinum aset_value2 (verinum::V1, ff2->width());
verinum sset_value2 (verinum::V1, ff2->width());
for (unsigned idx = 0 ; idx < ff2->width() ; idx += 1) { for (unsigned idx = 0 ; idx < ff2->width() ; idx += 1) {
unsigned ptr = find_nexus_in_set(nex_map, unsigned ptr = find_nexus_in_set(nex_map,
tmp_map->pin(idx).nexus()); tmp_map->pin(idx).nexus());
/* Connect Data and Q bits to the new FF. */
connect(ff->pin_Data(ptr), ff2->pin_Data(idx)); connect(ff->pin_Data(ptr), ff2->pin_Data(idx));
connect(ff->pin_Q(ptr), ff2->pin_Q(idx)); connect(ff->pin_Q(ptr), ff2->pin_Q(idx));
/* Copy the asynch set bit to the new device. */
if (ptr < tmp_aset.len()) if (ptr < tmp_aset.len())
aset_value2.set(idx, tmp_aset[ptr]); aset_value2.set(idx, tmp_aset[ptr]);
/* Copy the synch set bit to the new device. */
if (ptr < tmp_sset.len())
sset_value2.set(idx, tmp_sset[ptr]);
if (pin_accounting[ptr] != 0) { if (pin_accounting[ptr] != 0) {
cerr << cur->get_line() << ": error: " cerr << cur->get_line() << ": error: "
<< "Synchronous output conflicts with " << "Synchronous output conflicts with "
@ -417,10 +426,15 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
pin_accounting[ptr] = cur; pin_accounting[ptr] = cur;
} }
} }
if (ff->pin_Aclr().is_linked()) if (ff->pin_Aclr().is_linked())
connect(ff->pin_Aclr(), ff2->pin_Aclr()); connect(ff->pin_Aclr(), ff2->pin_Aclr());
if (ff->pin_Aset().is_linked()) if (ff->pin_Aset().is_linked())
connect(ff->pin_Aset(), ff2->pin_Aset()); connect(ff->pin_Aset(), ff2->pin_Aset());
if (ff->pin_Sclr().is_linked())
connect(ff->pin_Sclr(), ff2->pin_Sclr());
if (ff->pin_Sset().is_linked())
connect(ff->pin_Sset(), ff2->pin_Sset());
if (ff->pin_Clock().is_linked()) if (ff->pin_Clock().is_linked())
connect(ff->pin_Clock(), ff2->pin_Clock()); connect(ff->pin_Clock(), ff2->pin_Clock());
if (ff->pin_Enable().is_linked()) if (ff->pin_Enable().is_linked())
@ -560,6 +574,56 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, NetFF*ff,
delete expr_input; delete expr_input;
/* Detect the case that this is a *synchronous* set/reset. It
is not asyncronous because we know the condition is not
included in the sensitivity list, but if the if_ case is
constant (has no inputs) then we can model this as a
synchronous set/reset. */
NexusSet*a_set = if_->nex_input();
if (a_set->count() == 0) {
NetNet*rst = expr_->synthesize(des);
assert(rst->pin_count() == 1);
/* Synthesize the true clause to figure out what
kind of set/reset we have. */
NetNet*asig = new NetNet(scope, scope->local_symbol(),
NetNet::WIRE, nex_map->pin_count());
asig->local_flag(true);
bool flag = if_->synth_async(des, scope, nex_map, asig);
assert(asig->pin_count() == ff->width());
/* Collect the set/reset value into a verinum. If
this turns out to be entirely 0 values, then
use the Sclr input. Otherwise, use the Aset
input and save the set value. */
verinum tmp (verinum::V0, ff->width());
for (unsigned bit = 0 ; bit < ff->width() ; bit += 1) {
assert(asig->pin(bit).nexus()->drivers_constant());
tmp.set(bit, asig->pin(bit).nexus()->driven_value());
}
assert(tmp.is_defined());
if (tmp.is_zero()) {
connect(ff->pin_Sclr(), rst->pin(0));
} else {
connect(ff->pin_Sset(), rst->pin(0));
ff->sset_value(tmp);
}
delete a_set;
return else_->synth_sync(des, scope, ff, nex_map,
nex_out, svector<NetEvProbe*>(0))
&& flag;
}
delete a_set;
/* Failed to find an asynchronous set/reset, so any events /* Failed to find an asynchronous set/reset, so any events
input are probably in error. */ input are probably in error. */
if (events_in.count() > 0) { if (events_in.count() > 0) {
@ -813,6 +877,9 @@ void synth2(Design*des)
/* /*
* $Log: synth2.cc,v $ * $Log: synth2.cc,v $
* Revision 1.30 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.29 2003/08/14 02:41:05 steve * Revision 1.29 2003/08/14 02:41:05 steve
* Fix dangling pointer in NexusSet handling blocks. * Fix dangling pointer in NexusSet handling blocks.
* *

29
t-dll-api.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll-api.cc,v 1.101 2003/06/24 01:38:03 steve Exp $" #ident "$Id: t-dll-api.cc,v 1.102 2003/08/15 02:23:53 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -620,6 +620,18 @@ extern "C" ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net)
} }
} }
extern "C" ivl_nexus_t ivl_lpm_sync_clr(ivl_lpm_t net)
{
assert(net);
switch(net->type) {
case IVL_LPM_FF:
return net->u_.ff.sclr;
default:
assert(0);
return 0;
}
}
extern "C" ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net) extern "C" ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net)
{ {
assert(net); assert(net);
@ -632,6 +644,18 @@ extern "C" ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net)
} }
} }
extern "C" ivl_nexus_t ivl_lpm_sync_set(ivl_lpm_t net)
{
assert(net);
switch(net->type) {
case IVL_LPM_FF:
return net->u_.ff.sset;
default:
assert(0);
return 0;
}
}
extern "C" ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net) extern "C" ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net)
{ {
assert(net); assert(net);
@ -1848,6 +1872,9 @@ extern "C" ivl_variable_type_t ivl_variable_type(ivl_variable_t net)
/* /*
* $Log: t-dll-api.cc,v $ * $Log: t-dll-api.cc,v $
* Revision 1.102 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.101 2003/06/24 01:38:03 steve * Revision 1.101 2003/06/24 01:38:03 steve
* Various warnings fixed. * Various warnings fixed.
* *

15
t-dll.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll.cc,v 1.118 2003/07/30 01:13:28 steve Exp $" #ident "$Id: t-dll.cc,v 1.119 2003/08/15 02:23:53 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -1527,6 +1527,16 @@ void dll_target::lpm_ff(const NetFF*net)
obj->u_.ff.aset_value = 0; obj->u_.ff.aset_value = 0;
} }
if (net->pin_Sclr().is_linked()) {
nex = net->pin_Sclr().nexus();
assert(nex->t_cookie());
obj->u_.ff.sclr = (ivl_nexus_t) nex->t_cookie();
assert(obj->u_.ff.sclr);
nexus_lpm_add(obj->u_.ff.sclr, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
} else {
obj->u_.ff.sclr = 0;
}
if (obj->u_.ff.width == 1) { if (obj->u_.ff.width == 1) {
nex = net->pin_Q(0).nexus(); nex = net->pin_Q(0).nexus();
assert(nex->t_cookie()); assert(nex->t_cookie());
@ -2134,6 +2144,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
/* /*
* $Log: t-dll.cc,v $ * $Log: t-dll.cc,v $
* Revision 1.119 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.118 2003/07/30 01:13:28 steve * Revision 1.118 2003/07/30 01:13:28 steve
* Add support for triand and trior. * Add support for triand and trior.
* *

67
t-dll.h
View File

@ -1,7 +1,7 @@
#ifndef __t_dll_H #ifndef __t_dll_H
#define __t_dll_H #define __t_dll_H
/* /*
* Copyright (c) 2000-2002 Stephen Williams (steve@icarus.com) * Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: t-dll.h,v 1.104 2003/06/23 01:25:44 steve Exp $" #ident "$Id: t-dll.h,v 1.105 2003/08/15 02:23:53 steve Exp $"
#endif #endif
# include "target.h" # include "target.h"
@ -299,6 +299,8 @@ struct ivl_lpm_s {
ivl_nexus_t we; ivl_nexus_t we;
ivl_nexus_t aclr; ivl_nexus_t aclr;
ivl_nexus_t aset; ivl_nexus_t aset;
ivl_nexus_t sclr;
ivl_nexus_t sset;
union { union {
ivl_nexus_t*pins; ivl_nexus_t*pins;
ivl_nexus_t pin; ivl_nexus_t pin;
@ -681,6 +683,9 @@ struct ivl_variable_s {
/* /*
* $Log: t-dll.h,v $ * $Log: t-dll.h,v $
* Revision 1.105 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.104 2003/06/23 01:25:44 steve * Revision 1.104 2003/06/23 01:25:44 steve
* Module attributes make it al the way to ivl_target. * Module attributes make it al the way to ivl_target.
* *
@ -723,63 +728,5 @@ struct ivl_variable_s {
* *
* Revision 1.94 2002/09/26 03:18:04 steve * Revision 1.94 2002/09/26 03:18:04 steve
* Generate vvp code for asynch set/reset of NetFF. * Generate vvp code for asynch set/reset of NetFF.
*
* Revision 1.93 2002/08/12 01:35:01 steve
* conditional ident string using autoconfig.
*
* Revision 1.92 2002/08/07 02:36:10 steve
* Get local StringHeap.h
*
* Revision 1.91 2002/08/07 00:54:39 steve
* Add force to nets.
*
* Revision 1.90 2002/08/05 04:18:45 steve
* Store only the base name of memories.
*
* Revision 1.89 2002/08/04 19:13:16 steve
* dll uses StringHeap for named items.
*
* Revision 1.88 2002/08/04 18:28:15 steve
* Do not use hierarchical names of memories to
* generate vvp labels. -tdll target does not
* used hierarchical name string to look up the
* memory objects in the design.
*
* Revision 1.87 2002/07/05 21:26:17 steve
* Avoid emitting to vvp local net symbols.
*
* Revision 1.86 2002/06/21 04:59:35 steve
* Carry integerness throughout the compilation.
*
* Revision 1.85 2002/06/16 20:39:12 steve
* Normalize run-time index expressions for bit selects
*
* Revision 1.84 2002/06/16 19:19:16 steve
* Generate runtime code to normalize indices.
*
* Revision 1.83 2002/06/05 03:44:25 steve
* Add support for memory words in l-value of
* non-blocking assignments, and remove the special
* NetAssignMem_ and NetAssignMemNB classes.
*
* Revision 1.82 2002/06/04 05:38:44 steve
* Add support for memory words in l-value of
* blocking assignments, and remove the special
* NetAssignMem class.
*
* Revision 1.81 2002/05/29 22:05:55 steve
* Offset lvalue index expressions.
*
* Revision 1.80 2002/05/27 00:08:45 steve
* Support carrying the scope of named begin-end
* blocks down to the code generator, and have
* the vvp code generator use that to support disable.
*
* Revision 1.79 2002/05/26 01:39:03 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*/ */
#endif #endif

22
tgt-fpga/d-lpm.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: d-lpm.c,v 1.5 2003/08/10 16:42:23 steve Exp $" #ident "$Id: d-lpm.c,v 1.6 2003/08/15 02:23:53 steve Exp $"
#endif #endif
/* /*
@ -350,9 +350,10 @@ static void lpm_show_dff(ivl_lpm_t net)
unsigned idx; unsigned idx;
unsigned pin, wid = ivl_lpm_width(net); unsigned pin, wid = ivl_lpm_width(net);
sprintf(name, "fd%s%s%u", sprintf(name, "fd%s%s%s%u",
ivl_lpm_enable(net)? "ce" : "", ivl_lpm_enable(net)? "ce" : "",
ivl_lpm_async_clr(net)? "cl" : "", ivl_lpm_async_clr(net)? "cl" : "",
ivl_lpm_sync_clr(net)? "sc" : "",
wid); wid);
cell = edif_xlibrary_findcell(xlib, name); cell = edif_xlibrary_findcell(xlib, name);
@ -364,6 +365,8 @@ static void lpm_show_dff(ivl_lpm_t net)
nports += 1; nports += 1;
if (ivl_lpm_async_clr(net)) if (ivl_lpm_async_clr(net))
nports += 1; nports += 1;
if (ivl_lpm_sync_clr(net))
nports += 1;
cell = edif_xcell_create(xlib, strdup(name), nports); cell = edif_xcell_create(xlib, strdup(name), nports);
edif_cell_pstring(cell, "LPM_Type", "LPM_FF"); edif_cell_pstring(cell, "LPM_Type", "LPM_FF");
@ -392,6 +395,11 @@ static void lpm_show_dff(ivl_lpm_t net)
pin += 1; pin += 1;
} }
if (ivl_lpm_sync_clr(net)) {
edif_cell_portconfig(cell, pin, "Sclr", IVL_SIP_INPUT);
pin += 1;
}
edif_cell_portconfig(cell, pin, "Clock", IVL_SIP_INPUT); edif_cell_portconfig(cell, pin, "Clock", IVL_SIP_INPUT);
pin += 1; pin += 1;
@ -419,6 +427,13 @@ static void lpm_show_dff(ivl_lpm_t net)
edif_add_to_joint(jnt, ref, pin); edif_add_to_joint(jnt, ref, pin);
} }
if (ivl_lpm_sync_clr(net)) {
pin = edif_cell_port_byname(cell, "Sclr");
jnt = edif_joint_of_nexus(edf, ivl_lpm_sync_clr(net));
edif_add_to_joint(jnt, ref, pin);
}
for (idx = 0 ; idx < wid ; idx += 1) { for (idx = 0 ; idx < wid ; idx += 1) {
sprintf(name, "Q%u", idx); sprintf(name, "Q%u", idx);
@ -690,6 +705,9 @@ const struct device_s d_lpm_edif = {
/* /*
* $Log: d-lpm.c,v $ * $Log: d-lpm.c,v $
* Revision 1.6 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.5 2003/08/10 16:42:23 steve * Revision 1.5 2003/08/10 16:42:23 steve
* Add async clear to LPM_FF devices. * Add async clear to LPM_FF devices.
* *

19
tgt-fpga/d-virtex.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: d-virtex.c,v 1.31 2003/07/04 00:10:09 steve Exp $" #ident "$Id: d-virtex.c,v 1.32 2003/08/15 02:23:53 steve Exp $"
#endif #endif
# include "device.h" # include "device.h"
@ -249,6 +249,8 @@ void virtex_generic_dff(ivl_lpm_t net)
ivl_nexus_t aclr = ivl_lpm_async_clr(net); ivl_nexus_t aclr = ivl_lpm_async_clr(net);
ivl_nexus_t aset = ivl_lpm_async_set(net); ivl_nexus_t aset = ivl_lpm_async_set(net);
ivl_nexus_t sclr = ivl_lpm_sync_clr(net);
ivl_nexus_t sset = ivl_lpm_sync_set(net);
const char*abits = 0; const char*abits = 0;
if (aset) { if (aset) {
@ -258,6 +260,10 @@ void virtex_generic_dff(ivl_lpm_t net)
assert(abits); assert(abits);
} }
/* XXXX Can't handle both synchronous and asynchronous clear. */
assert( ! (aclr && sclr) );
/* XXXX Can't handle synchronous set at all. */
assert( ! sset );
for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) { for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
edif_cellref_t obj; edif_cellref_t obj;
@ -268,10 +274,15 @@ void virtex_generic_dff(ivl_lpm_t net)
an FDCE device. */ an FDCE device. */
if (aset && (abits[idx] == '1')) { if (aset && (abits[idx] == '1')) {
obj = edif_cellref_create(edf, xilinx_cell_fdcpe(xlib)); obj = edif_cellref_create(edf, xilinx_cell_fdcpe(xlib));
} else if (aclr) {
obj = edif_cellref_create(edf, xilinx_cell_fdce(xlib));
} else if (sclr) {
obj = edif_cellref_create(edf, xilinx_cell_fdre(xlib));
} else { } else {
obj = edif_cellref_create(edf, xilinx_cell_fdce(xlib)); obj = edif_cellref_create(edf, xilinx_cell_fdce(xlib));
} }
jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx)); jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
edif_add_to_joint(jnt, obj, FDCE_Q); edif_add_to_joint(jnt, obj, FDCE_Q);
@ -289,6 +300,9 @@ void virtex_generic_dff(ivl_lpm_t net)
if (aclr) { if (aclr) {
jnt = edif_joint_of_nexus(edf, aclr); jnt = edif_joint_of_nexus(edf, aclr);
edif_add_to_joint(jnt, obj, FDCE_CLR); edif_add_to_joint(jnt, obj, FDCE_CLR);
} else if (sclr) {
jnt = edif_joint_of_nexus(edf, sclr);
edif_add_to_joint(jnt, obj, FDCE_CLR);
} }
if (aset) { if (aset) {
@ -831,6 +845,9 @@ const struct device_s d_virtex_edif = {
/* /*
* $Log: d-virtex.c,v $ * $Log: d-virtex.c,v $
* Revision 1.32 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.31 2003/07/04 00:10:09 steve * Revision 1.31 2003/07/04 00:10:09 steve
* Generate MUXF5 based 4-input N-wide muxes. * Generate MUXF5 based 4-input N-wide muxes.
* *

19
tgt-fpga/xilinx.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: xilinx.c,v 1.9 2003/07/04 01:08:03 steve Exp $" #ident "$Id: xilinx.c,v 1.10 2003/08/15 02:23:53 steve Exp $"
#endif #endif
# include "edif.h" # include "edif.h"
@ -206,6 +206,20 @@ edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib)
return cell; return cell;
} }
edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib)
{
static edif_cell_t cell = 0;
if (cell != 0) return cell;
cell = edif_xcell_create(xlib, "FDRE", 5);
edif_cell_portconfig(cell, FDCE_Q, "Q", IVL_SIP_INPUT);
edif_cell_portconfig(cell, FDCE_D, "D", IVL_SIP_OUTPUT);
edif_cell_portconfig(cell, FDCE_C, "C", IVL_SIP_INPUT);
edif_cell_portconfig(cell, FDCE_CE, "CE", IVL_SIP_INPUT);
edif_cell_portconfig(cell, FDCE_CLR,"R", IVL_SIP_INPUT);
return cell;
}
edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib) edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib)
{ {
@ -937,6 +951,9 @@ void xilinx_shiftl(ivl_lpm_t net)
/* /*
* $Log: xilinx.c,v $ * $Log: xilinx.c,v $
* Revision 1.10 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.9 2003/07/04 01:08:03 steve * Revision 1.9 2003/07/04 01:08:03 steve
* PAD attribute can be used to assign pins. * PAD attribute can be used to assign pins.
* *

9
tgt-fpga/xilinx.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: xilinx.h,v 1.7 2003/07/04 00:10:09 steve Exp $" #ident "$Id: xilinx.h,v 1.8 2003/08/15 02:23:53 steve Exp $"
#endif #endif
/* /*
@ -67,8 +67,12 @@ extern edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib);
/* === Flip-Flop Devices === */ /* === Flip-Flop Devices === */
/*
* These are flip-flops of various sort, but similar pinouts.
*/
extern edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib); extern edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib);
extern edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib); extern edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib);
extern edif_cell_t xilinx_cell_fdre(edif_xlibrary_t xlib);
#define FDCE_Q 0 #define FDCE_Q 0
#define FDCE_C 1 #define FDCE_C 1
#define FDCE_D 2 #define FDCE_D 2
@ -126,6 +130,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
/* /*
* $Log: xilinx.h,v $ * $Log: xilinx.h,v $
* Revision 1.8 2003/08/15 02:23:53 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.7 2003/07/04 00:10:09 steve * Revision 1.7 2003/07/04 00:10:09 steve
* Generate MUXF5 based 4-input N-wide muxes. * Generate MUXF5 based 4-input N-wide muxes.
* *

6
verilog.spec
View File

@ -1,10 +1,10 @@
Summary: Icarus Verilog Summary: Icarus Verilog
Name: verilog Name: verilog
Version: 0.7.20030730 Version: 0.7.20030810
Release: 0 Release: 0
Copyright: GPL Copyright: GPL
Group: Applications/Engineering Group: Applications/Engineering
Source: ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20030730.tar.gz Source: ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20030810.tar.gz
URL: http://www.icarus.com/eda/verilog/index.html URL: http://www.icarus.com/eda/verilog/index.html
Packager: Stephen Williams <steve@icarus.com> Packager: Stephen Williams <steve@icarus.com>
@ -22,7 +22,7 @@ engineering formats, including simulation. It strives to be true
to the IEEE-1364 standard. to the IEEE-1364 standard.
%prep %prep
%setup -n verilog-20030730 %setup -n verilog-20030810
%build %build
%ifarch x86_64 %ifarch x86_64