Replace AND constand propagation.
This commit is contained in:
steve
parent
2750977e4a
commit
e05b9a4769
158
cprop.cc
158
cprop.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: cprop.cc,v 1.20 2000/11/18 05:13:27 steve Exp $"
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#ident "$Id: cprop.cc,v 1.21 2000/11/19 05:26:58 steve Exp $"
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#endif
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# include "netlist.h"
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@ -184,45 +184,152 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
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{
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switch (obj->type()) {
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case NetLogic::AND:
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// If there is one zero input to an AND gate, we know
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// the resulting output is going to be zero and can
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// elininate the gate.
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for (unsigned idx = 1 ; idx < obj->pin_count() ; idx += 1) {
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if (! link_drivers_constant(obj->pin(idx)))
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case NetLogic::NAND:
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case NetLogic::AND: {
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unsigned top = obj->pin_count();
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unsigned idx = 1;
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unsigned xs = 0;
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/* Eliminate all the 1 inputs. They have no effect
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on the output of an AND gate. */
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while (idx < top) {
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if (! link_drivers_constant(obj->pin(idx))) {
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idx += 1;
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continue;
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if (driven_value(obj->pin(idx)) == verinum::V0) {
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connect(obj->pin(0), obj->pin(idx));
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}
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if (driven_value(obj->pin(idx)) == verinum::V1) {
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obj->pin(idx).unlink();
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top -= 1;
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if (idx < top) {
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connect(obj->pin(idx), obj->pin(top));
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obj->pin(top).unlink();
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}
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continue;
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}
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if (driven_value(obj->pin(idx)) != verinum::V0) {
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idx += 1;
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xs += 1;
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continue;
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}
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/* Oops! We just stumbled on a driven-0 input
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to the AND gate. That means we can replace
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the whole bloody thing with a constant
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driver and exit now. */
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NetConst*tmp;
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switch (obj->type()) {
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case NetLogic::AND:
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tmp = new NetConst(obj->name(), verinum::V0);
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break;
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case NetLogic::NAND:
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tmp = new NetConst(obj->name(), verinum::V1);
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break;
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default:
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assert(0);
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}
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des->add_node(tmp);
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tmp->pin(0).drive0(obj->pin(0).drive0());
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tmp->pin(0).drive1(obj->pin(0).drive1());
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connect(obj->pin(0), tmp->pin(0));
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delete obj;
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count += 1;
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return;
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}
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/* If all the inputs were eliminated, then replace
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the gate with a constant 1 and I am done. */
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if (top == 1) {
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NetConst*tmp;
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switch (obj->type()) {
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case NetLogic::AND:
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tmp = new NetConst(obj->name(), verinum::V1);
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break;
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case NetLogic::NAND:
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tmp = new NetConst(obj->name(), verinum::V0);
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break;
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default:
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assert(0);
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}
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// There are no zero constant drivers. If there are any
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// non-constant drivers, give up.
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for (unsigned idx = 1 ; idx < obj->pin_count() ; idx += 1) {
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if (! link_drivers_constant(obj->pin(idx)))
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return;
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}
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des->add_node(tmp);
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tmp->pin(0).drive0(obj->pin(0).drive0());
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tmp->pin(0).drive1(obj->pin(0).drive1());
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connect(obj->pin(0), tmp->pin(0));
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// If there are any non-1 values (Vx or Vz) then the
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// result is Vx.
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for (unsigned idx = 1 ; idx < obj->pin_count() ; idx += 1) {
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if (driven_value(obj->pin(idx)) != verinum::V1) {
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connect(obj->pin(0), obj->pin(idx));
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delete obj;
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count += 1;
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return;
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}
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}
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// What's left? The inputs are all 1's, return the first
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// input as the output value and remove the gate.
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connect(obj->pin(0), obj->pin(1));
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/* If all the inputs are unknowns, then replace the
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gate with a Vx. */
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if (xs == (top-1)) {
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NetConst*tmp;
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tmp = new NetConst(obj->name(), verinum::Vx);
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des->add_node(tmp);
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tmp->pin(0).drive0(obj->pin(0).drive0());
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tmp->pin(0).drive1(obj->pin(0).drive1());
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connect(obj->pin(0), tmp->pin(0));
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delete obj;
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count += 1;
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return;
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}
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/* If we are down to only one input, then replace
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the AND with a BUF and exit now. */
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if (top == 2) {
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NetLogic*tmp;
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switch (obj->type()) {
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case NetLogic::AND:
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tmp = new NetLogic(obj->scope(),
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obj->name(), 2,
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NetLogic::BUF);
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break;
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case NetLogic::NAND:
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tmp = new NetLogic(obj->scope(),
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obj->name(), 2,
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NetLogic::NOT);
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break;
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default:
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assert(0);
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}
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des->add_node(tmp);
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tmp->pin(0).drive0(obj->pin(0).drive0());
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tmp->pin(0).drive1(obj->pin(0).drive1());
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connect(obj->pin(0), tmp->pin(0));
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connect(obj->pin(1), tmp->pin(1));
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delete obj;
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count += 1;
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return;
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}
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/* Finally, this cleans up the gate by creating a
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new [N]OR gate that has the right number of
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inputs, connected in the right place. */
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if (top < obj->pin_count()) {
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NetLogic*tmp = new NetLogic(obj->scope(),
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obj->name(), top,
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obj->type());
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des->add_node(tmp);
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tmp->pin(0).drive0(obj->pin(0).drive0());
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tmp->pin(0).drive1(obj->pin(0).drive1());
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for (unsigned idx = 0 ; idx < top ; idx += 1)
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connect(tmp->pin(idx), obj->pin(idx));
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delete obj;
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count += 1;
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return;
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}
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break;
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}
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case NetLogic::NOR:
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case NetLogic::OR: {
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@ -662,6 +769,9 @@ void cprop(Design*des)
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/*
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* $Log: cprop.cc,v $
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* Revision 1.21 2000/11/19 05:26:58 steve
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* Replace AND constand propagation.
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*
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* Revision 1.20 2000/11/18 05:13:27 steve
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* Thorough constant propagation for or and nor gates.
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*
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