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draw proper signal references for the gates.

This commit is contained in:
steve 2000-10-26 16:42:25 +00:00
parent 26350fdcf5
commit df660bab0c
1 changed files with 48 additions and 15 deletions
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63
tgt-verilog/verilog.c
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@ -17,20 +17,20 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: verilog.c,v 1.15 2000/10/26 00:32:28 steve Exp $" #ident "$Id: verilog.c,v 1.16 2000/10/26 16:42:25 steve Exp $"
#endif #endif
/* /*
* This is a sample target module. All this does is write to the * This target writes a Verilog description of the design. The output
* output file some information about each object handle when each of * Verilog is a single module that has the name of the root module of
* the various object functions is called. This can be used to * the design, but is internally the complete design.
* understand the behavior of the core as it uses a target module.
*/ */
# include <ivl_target.h> # include <ivl_target.h>
# include <stdio.h> # include <stdio.h>
# include <assert.h> # include <assert.h>
/* This is the output file where the verilog program is sent. */
static FILE*out; static FILE*out;
/* /*
@ -62,6 +62,36 @@ static void draw_scoped_objects(ivl_design_t des)
} }
/*
* Given a nexus, this function draws a signal reference. We don't
* care really whether the signal is a reg or wire, because this may
* be an input or output of a gate. Just print it. And if this is a
* bit of a vector, draw the bit select needed to get at the right bit.
*/
static void draw_nexus(ivl_nexus_t nex)
{
ivl_signal_t sig;
ivl_nexus_ptr_t ptr;
unsigned idx;
for (idx = 0 ; idx < ivl_nexus_ptrs(nex) ; idx += 1) {
ptr = ivl_nexus_ptr(nex, idx);
sig = ivl_nexus_ptr_sig(ptr);
if (sig)
break;
}
assert(sig);
if (ivl_signal_pins(sig) == 1) {
fprintf(out, "%s", ivl_signal_name(sig));
} else {
fprintf(out, "%s[%u]", ivl_signal_name(sig),
ivl_nexus_ptr_pin(ptr));
}
}
/* /*
* Draw a single logic gate. Escape the name so that it is preserved * Draw a single logic gate. Escape the name so that it is preserved
* completely. This drawing is happening in the root scope so signal * completely. This drawing is happening in the root scope so signal
@ -74,29 +104,29 @@ static int draw_logic(ivl_net_logic_t net)
switch (ivl_logic_type(net)) { switch (ivl_logic_type(net)) {
case IVL_LO_AND: case IVL_LO_AND:
fprintf(out, " and \\%s (%s", name, fprintf(out, " and \\%s (", name);
ivl_nexus_name(ivl_logic_pin(net, 0)));
break; break;
case IVL_LO_BUF: case IVL_LO_BUF:
fprintf(out, " buf \\%s (%s", name, fprintf(out, " buf \\%s (", name);
ivl_nexus_name(ivl_logic_pin(net, 0)));
break; break;
case IVL_LO_OR: case IVL_LO_OR:
fprintf(out, " or \\%s (%s", name, fprintf(out, " or \\%s (", name);
ivl_nexus_name(ivl_logic_pin(net, 0)));
break; break;
case IVL_LO_XOR: case IVL_LO_XOR:
fprintf(out, " xor \\%s (%s", name, fprintf(out, " xor \\%s (", name);
ivl_nexus_name(ivl_logic_pin(net, 0)));
break; break;
default: default:
fprintf(out, "STUB: %s: unsupported gate\n", name); fprintf(out, "STUB: %s: unsupported gate\n", name);
return -1; return -1;
} }
draw_nexus(ivl_logic_pin(net, 0));
npins = ivl_logic_pins(net); npins = ivl_logic_pins(net);
for (idx = 1 ; idx < npins ; idx += 1) for (idx = 1 ; idx < npins ; idx += 1) {
fprintf(out, ", %s", ivl_nexus_name(ivl_logic_pin(net,idx))); fprintf(out, ", ");
draw_nexus(ivl_logic_pin(net,idx));
}
fprintf(out, ");\n"); fprintf(out, ");\n");
return 0; return 0;
@ -365,6 +395,9 @@ DECLARE_CYGWIN_DLL(DllMain);
/* /*
* $Log: verilog.c,v $ * $Log: verilog.c,v $
* Revision 1.16 2000/10/26 16:42:25 steve
* draw proper signal references for the gates.
*
* Revision 1.15 2000/10/26 00:32:28 steve * Revision 1.15 2000/10/26 00:32:28 steve
* emit declarations of signals and gates. * emit declarations of signals and gates.
* *