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Fix broken example code (discussion #922) 

'output' is a keyword, so can't be used as a signal name.
This commit is contained in:
Martin Whitaker 2023-05-15 19:42:47 +01:00
parent b210eb8264
commit deeac2edfe
1 changed files with 4 additions and 4 deletions
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8
Documentation/usage/getting_started.rst
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@ -65,11 +65,11 @@ example, the counter model in counter.v
.. code-block:: verilog .. code-block:: verilog
module counter(output, clk, reset); module counter(out, clk, reset);
parameter WIDTH = 8; parameter WIDTH = 8;
output [WIDTH-1 : 0] output; output [WIDTH-1 : 0] out;
input clk, reset; input clk, reset;
reg [WIDTH-1 : 0] out; reg [WIDTH-1 : 0] out;
@ -77,9 +77,9 @@ example, the counter model in counter.v
always @(posedge clk or posedge reset) always @(posedge clk or posedge reset)
if (reset) if (reset)
output <= 0; out <= 0;
else else
output <= output + 1; out <= out + 1;
endmodule // counter endmodule // counter