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Fix most of the cppcheck warnings in the vhdlpp directory. 

Mostly using size() vs empty() in the STL and a missing initialization.
This commit is contained in:
Cary R 2011-07-28 17:07:49 -07:00 committed by Stephen Williams
parent 836e61e878
commit de356b03c8
9 changed files with 12 additions and 11 deletions
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2
vhdlpp/architec_emit.cc
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@ -126,7 +126,7 @@ int ProcessStatement::emit(ostream&out, Entity*ent, Architecture*arc)
out << "always"; out << "always";
if (sensitivity_list_.size() > 0) { if (! sensitivity_list_.empty()) {
out << " @("; out << " @(";
const char*comma = 0; const char*comma = 0;
for (list<Expression*>::iterator cur = sensitivity_list_.begin() for (list<Expression*>::iterator cur = sensitivity_list_.begin()

2
vhdlpp/debug.cc
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@ -57,7 +57,7 @@ void dump_design_entities(ostream&file)
void ComponentBase::dump_ports(ostream&out, int indent) const void ComponentBase::dump_ports(ostream&out, int indent) const
{ {
if (ports_.size() == 0) { if (ports_.empty()) {
out << setw(indent) << "" << "No ports" << endl; out << setw(indent) << "" << "No ports" << endl;
} else { } else {
out << setw(indent) << "" << "PORTS:" << endl; out << setw(indent) << "" << "PORTS:" << endl;

3
vhdlpp/entity.cc
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@ -40,7 +40,7 @@ ComponentBase::~ComponentBase()
void ComponentBase::set_interface(std::list<InterfacePort*>*ports) void ComponentBase::set_interface(std::list<InterfacePort*>*ports)
{ {
while (ports->size() > 0) { while (! ports->empty()) {
ports_.push_back(ports->front()); ports_.push_back(ports->front());
ports->pop_front(); ports->pop_front();
} }
@ -59,6 +59,7 @@ const InterfacePort* ComponentBase::find_port(perm_string my_name) const
Entity::Entity(perm_string name) Entity::Entity(perm_string name)
: ComponentBase(name) : ComponentBase(name)
{ {
bind_arch_ = 0;
} }
Entity::~Entity() Entity::~Entity()

2
vhdlpp/entity.h
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@ -73,7 +73,7 @@ class ComponentBase : public LineInfo {
protected: protected:
// This is really only used by the Entity derived class. // This is really only used by the Entity derived class.
const std::vector<InterfacePort*>&get_ports() { return ports_; } const std::vector<InterfacePort*>&get_ports() const { return ports_; }
private: private:
perm_string name_; perm_string name_;

2
vhdlpp/entity_elaborate.cc
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@ -49,7 +49,7 @@ int Entity::elaborate()
if (verbose_flag) if (verbose_flag)
cerr << "Elaborate entity " << get_name() << "..." << endl; cerr << "Elaborate entity " << get_name() << "..." << endl;
if (arch_.size() == 0) { if (arch_.empty()) {
cerr << get_fileline() << ": error: " cerr << get_fileline() << ": error: "
<< "No architectures to choose from for entity " << get_name() << "No architectures to choose from for entity " << get_name()
<< "." << endl; << "." << endl;

2
vhdlpp/parse.y
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@ -97,7 +97,7 @@ static void push_scope(void)
static void pop_scope(void) static void pop_scope(void)
{ {
delete active_scope; delete active_scope;
assert(scope_stack.size() > 0); assert(! scope_stack.empty());
active_scope = scope_stack.top(); active_scope = scope_stack.top();
scope_stack.pop(); scope_stack.pop();
} }

4
vhdlpp/sequential.cc
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@ -61,7 +61,7 @@ IfSequential::~IfSequential()
void IfSequential::extract_true(std::list<SequentialStmt*>&that) void IfSequential::extract_true(std::list<SequentialStmt*>&that)
{ {
while (if_.size() > 0) { while (! if_.empty()) {
that.push_back(if_.front()); that.push_back(if_.front());
if_.pop_front(); if_.pop_front();
} }
@ -69,7 +69,7 @@ void IfSequential::extract_true(std::list<SequentialStmt*>&that)
void IfSequential::extract_false(std::list<SequentialStmt*>&that) void IfSequential::extract_false(std::list<SequentialStmt*>&that)
{ {
while (else_.size() > 0) { while (! else_.empty()) {
that.push_back(else_.front()); that.push_back(else_.front());
else_.pop_front(); else_.pop_front();
} }

2
vhdlpp/sequential_emit.cc
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@ -49,7 +49,7 @@ int IfSequential::emit(ostream&out, Entity*ent, Architecture*arc)
errors += (*cur)->statement_emit(out, ent, arc); errors += (*cur)->statement_emit(out, ent, arc);
} }
if (else_.size() > 0) { if (! else_.empty()) {
out << "end else begin" << endl; out << "end else begin" << endl;
for (list<SequentialStmt*>::iterator cur = else_.begin() for (list<SequentialStmt*>::iterator cur = else_.begin()

4
vhdlpp/vtype_stream.cc
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@ -33,7 +33,7 @@ void VTypeArray::write_to_stream(ostream&fd) const
// Special case: std_logic_vector // Special case: std_logic_vector
if (etype_ == primitive_STDLOGIC) { if (etype_ == primitive_STDLOGIC) {
fd << "std_logic_vector"; fd << "std_logic_vector";
if (ranges_.size() > 0) { if (! ranges_.empty()) {
assert(ranges_.size() < 2); assert(ranges_.size() < 2);
fd << " (" << ranges_[0].msb() fd << " (" << ranges_[0].msb()
<< " downto " << ranges_[0].lsb() << ") "; << " downto " << ranges_[0].lsb() << ") ";
@ -42,7 +42,7 @@ void VTypeArray::write_to_stream(ostream&fd) const
} }
fd << "array "; fd << "array ";
if (ranges_.size() > 0) { if (! ranges_.empty()) {
assert(ranges_.size() < 2); assert(ranges_.size() < 2);
fd << "(" << ranges_[0].msb() fd << "(" << ranges_[0].msb()
<< " downto " << ranges_[0].lsb() << ") "; << " downto " << ranges_[0].lsb() << ") ";