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Added new vvp latch statement to README file.

This commit is contained in:
Martin Whitaker 2016-03-12 12:14:03 +00:00
parent 9d487c6951
commit dc189fec8c
1 changed files with 10 additions and 1 deletions
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11
vvp/README.txt
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@ -195,7 +195,7 @@ combining up to four inputs down to one output.
B | * * 1 B | * * 1
DFF STATEMENTS: DFF AND LATCH STATEMENTS:
The Verilog language itself does not have a DFF primitive, but post The Verilog language itself does not have a DFF primitive, but post
synthesis readily creates DFF devices that are best simulated with a synthesis readily creates DFF devices that are best simulated with a
@ -219,6 +219,15 @@ rising edge causes the device to clear/set, forces the output to
propagate, and disables the clock until the aynchronous input is propagate, and disables the clock until the aynchronous input is
deasserted. Thus, they implement DFF with asynchronous clr or set. deasserted. Thus, they implement DFF with asynchronous clr or set.
Similarly, synthesis creates D-type latches, so there is the LATCH
statement to support this:
<label> .latch <width> <d>, <en>;
The <en> is a single bit vector (or scalar) on port-1. Port-0 is any
type of datum at all. The device will transfer the input to the output
whenever <en> is a logic 1.
UDP STATEMENTS: UDP STATEMENTS: