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Fix for br1015 : assertion failure when task/function port is an array. 

This is an error for Verilog and not yet supported for SystemVerilog.

(cherry picked from commit e97883b1db)
This commit is contained in:
Martin Whitaker 2019-08-02 15:34:31 +01:00
parent 2546631874
commit dbcb7e5fb6
2 changed files with 10 additions and 1 deletions
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5
elab_sig.cc
View File

@ -757,6 +757,11 @@ void PTaskFunc::elaborate_sig_ports_(Design*des, NetScope*scope,
<< "Function arguments must be input ports." << endl; << "Function arguments must be input ports." << endl;
des->errors += 1; des->errors += 1;
} }
if (tmp->unpacked_dimensions() != 0) {
cerr << get_fileline() << ": sorry: Subroutine ports with "
"unpacked dimensions are not yet supported." << endl;
des->errors += 1;
}
} }
} }

6
parse.y
View File

@ -2212,7 +2212,11 @@ tf_port_item /* IEEE1800-2005: A.2.7 */
tmp = pform_make_task_ports(@3, use_port_type, $2, ilist); tmp = pform_make_task_ports(@3, use_port_type, $2, ilist);
} }
if ($4 != 0) { if ($4 != 0) {
pform_set_reg_idx(name, $4); if (gn_system_verilog()) {
pform_set_reg_idx(name, $4);
} else {
yyerror(@4, "error: Task/function port with unpacked dimensions requires SystemVerilog.");
}
} }
$$ = tmp; $$ = tmp;