luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Do not change reg to wire in NetAssign_ unless synthesizing.

This commit is contained in:
steve 2004-08-28 15:08:31 +00:00
parent 21ba781604
commit d76ad25778
4 changed files with 48 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
net_assign.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: net_assign.cc,v 1.17 2004/02/18 17:11:56 steve Exp $" #ident "$Id: net_assign.cc,v 1.18 2004/08/28 15:08:31 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -67,7 +67,7 @@ NetAssign_::~NetAssign_()
{ {
if (sig_) { if (sig_) {
sig_->decr_lref(); sig_->decr_lref();
if (sig_->peek_lref() == 0) if (turn_sig_to_wire_on_release_ && sig_->peek_lref() == 0)
sig_->type(NetNet::WIRE); sig_->type(NetNet::WIRE);
} }
@ -142,6 +142,13 @@ unsigned NetAssign_::get_loff() const
return loff_; return loff_;
} }
/*
*/
void NetAssign_::turn_sig_to_wire_on_release()
{
turn_sig_to_wire_on_release_ = true;
}
NetAssignBase::NetAssignBase(NetAssign_*lv, NetExpr*rv) NetAssignBase::NetAssignBase(NetAssign_*lv, NetExpr*rv)
: lval_(lv), rval_(rv), delay_(0) : lval_(lv), rval_(rv), delay_(0)
{ {
@ -254,6 +261,9 @@ NetAssignNB::~NetAssignNB()
/* /*
* $Log: net_assign.cc,v $ * $Log: net_assign.cc,v $
* Revision 1.18 2004/08/28 15:08:31 steve
* Do not change reg to wire in NetAssign_ unless synthesizing.
*
* Revision 1.17 2004/02/18 17:11:56 steve * Revision 1.17 2004/02/18 17:11:56 steve
* Use perm_strings for named langiage items. * Use perm_strings for named langiage items.
* *
@ -292,37 +302,5 @@ NetAssignNB::~NetAssignNB()
* Redo handling of assignment internal delays. * Redo handling of assignment internal delays.
* Leave it possible for them to be calculated * Leave it possible for them to be calculated
* at run time. * at run time.
*
* Revision 1.8 2001/08/25 23:50:03 steve
* Change the NetAssign_ class to refer to the signal
* instead of link into the netlist. This is faster
* and uses less space. Make the NetAssignNB carry
* the delays instead of the NetAssign_ lval objects.
*
* Change the vvp code generator to support multiple
* l-values, i.e. concatenations of part selects.
*
* Revision 1.7 2001/07/25 03:10:49 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.6 2000/10/18 20:04:39 steve
* Add ivl_lval_t and support for assignment l-values.
*
* Revision 1.5 2000/09/20 02:53:15 steve
* Correctly measure comples l-values of assignments.
*
* Revision 1.4 2000/09/10 02:18:16 steve
* elaborate complex l-values
*
* Revision 1.3 2000/09/07 00:06:53 steve
* encapsulate access to the l-value expected width.
*
* Revision 1.2 2000/09/02 23:40:13 steve
* Pull NetAssign_ creation out of constructors.
*
* Revision 1.1 2000/09/02 20:54:20 steve
* Rearrange NetAssign to make NetAssign_ separate.
*
*/ */

11
netlist.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.h,v 1.315 2004/06/30 15:32:18 steve Exp $" #ident "$Id: netlist.h,v 1.316 2004/08/28 15:08:31 steve Exp $"
#endif #endif
/* /*
@ -1427,6 +1427,11 @@ class NetAssign_ {
NetMemory*mem() const; NetMemory*mem() const;
NetVariable*var() const; NetVariable*var() const;
// Mark that the synthesizer has worked with this l-value, so
// when it is released, the l-value signal should be turned
// into a wire.
void turn_sig_to_wire_on_release();
// This pointer is for keeping simple lists. // This pointer is for keeping simple lists.
NetAssign_* more; NetAssign_* more;
@ -1438,6 +1443,7 @@ class NetAssign_ {
NetVariable*var_; NetVariable*var_;
NetExpr*bmux_; NetExpr*bmux_;
bool turn_sig_to_wire_on_release_;
unsigned loff_; unsigned loff_;
unsigned lwid_; unsigned lwid_;
}; };
@ -3343,6 +3349,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/* /*
* $Log: netlist.h,v $ * $Log: netlist.h,v $
* Revision 1.316 2004/08/28 15:08:31 steve
* Do not change reg to wire in NetAssign_ unless synthesizing.
*
* Revision 1.315 2004/06/30 15:32:18 steve * Revision 1.315 2004/06/30 15:32:18 steve
* nex_output for NetPDelay statements. * nex_output for NetPDelay statements.
* *

16
syn-rules.y
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: syn-rules.y,v 1.29 2004/02/20 18:53:35 steve Exp $" #ident "$Id: syn-rules.y,v 1.30 2004/08/28 15:08:32 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -131,6 +131,13 @@ static void hookup_DFF_CE(NetFF*ff, NetESignal*d, NetEvProbe*pclk,
if (pclk->edge() == NetEvProbe::NEGEDGE) if (pclk->edge() == NetEvProbe::NEGEDGE)
ff->attribute(perm_string::literal("Clock:LPM_Polarity"), verinum("INVERT")); ff->attribute(perm_string::literal("Clock:LPM_Polarity"), verinum("INVERT"));
/* This lval_ represents a reg that is a WIRE in the
synthesized results. This function signals the destructor
to change the REG that this l-value refers to into a
WIRE. It is done then, at the last minute, so that pending
synthesis can continue to work with it as a WIRE. */
a->turn_sig_to_wire_on_release();
} }
static void hookup_RAMDQ(NetRamDq*ram, NetESignal*d, NetNet*adr, static void hookup_RAMDQ(NetRamDq*ram, NetESignal*d, NetNet*adr,
@ -163,6 +170,13 @@ static void hookup_RAMDQ(NetRamDq*ram, NetESignal*d, NetNet*adr,
same NetMemory, that have the same address pins and are same NetMemory, that have the same address pins and are
otherwise compatible. This absorbs them into this object. */ otherwise compatible. This absorbs them into this object. */
ram->absorb_partners(); ram->absorb_partners();
/* This lval_ represents a reg that is a WIRE in the
synthesized results. This function signals the destructor
to change the REG that this l-value refers to into a
WIRE. It is done then, at the last minute, so that pending
synthesis can continue to work with it as a WIRE. */
a->turn_sig_to_wire_on_release();
} }
static void make_DFF_CE(Design*des, NetProcTop*top, NetEvWait*wclk, static void make_DFF_CE(Design*des, NetProcTop*top, NetEvWait*wclk,

12
synth2.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: synth2.cc,v 1.37 2004/03/15 18:40:12 steve Exp $" #ident "$Id: synth2.cc,v 1.38 2004/08/28 15:08:32 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -115,6 +115,13 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope,
connect(nex_out->pin(ptr), rsig->pin(idx)); connect(nex_out->pin(ptr), rsig->pin(idx));
} }
/* This lval_ represents a reg that is a WIRE in the
synthesized results. This function signals the destructor
to change the REG that this l-value refers to into a
WIRE. It is done then, at the last minute, so that pending
synthesis can continue to work with it as a WIRE. */
lval_->turn_sig_to_wire_on_release();
DEBUG_SYNTH2_EXIT("NetAssignBase",true) DEBUG_SYNTH2_EXIT("NetAssignBase",true)
return true; return true;
} }
@ -978,6 +985,9 @@ void synth2(Design*des)
/* /*
* $Log: synth2.cc,v $ * $Log: synth2.cc,v $
* Revision 1.38 2004/08/28 15:08:32 steve
* Do not change reg to wire in NetAssign_ unless synthesizing.
*
* Revision 1.37 2004/03/15 18:40:12 steve * Revision 1.37 2004/03/15 18:40:12 steve
* Only include DEBUG_SYNTH2 if __FUNCTION__ defined. * Only include DEBUG_SYNTH2 if __FUNCTION__ defined.
* *