luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Allow assign to not match rvalue width.

This commit is contained in:
steve 1999-09-08 04:05:30 +00:00
parent 9d82d19d07
commit d6fbc30cd5
3 changed files with 17 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
elaborate.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: elaborate.cc,v 1.79 1999/09/08 02:24:39 steve Exp $"
#ident "$Id: elaborate.cc,v 1.80 1999/09/08 04:05:30 steve Exp $"
#endif
/*
@ -1417,13 +1417,7 @@ NetProc* PAssign::elaborate(Design*des, const string&path) const
if (mux == 0) {
unsigned wid = msb - lsb + 1;
if (! rv->set_width(wid)) {
cerr << get_line() << ": Unable to match expression "
"width of " << rv->expr_width() << " to l-value"
" width of " << wid << "." << endl;
//XXXX delete rv;
return 0;
}
rv->set_width(wid);
cur = new NetAssign(des->local_symbol(path), des, wid, rv);
for (unsigned idx = 0 ; idx < wid ; idx += 1)
@ -2186,6 +2180,9 @@ Design* elaborate(const map<string,Module*>&modules,
/*
* $Log: elaborate.cc,v $
* Revision 1.80 1999/09/08 04:05:30 steve
* Allow assign to not match rvalue width.
*
* Revision 1.79 1999/09/08 02:24:39 steve
* Empty conditionals (pmonta@imedia.com)
*

12
netlist.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: netlist.cc,v 1.57 1999/09/04 01:57:15 steve Exp $"
#ident "$Id: netlist.cc,v 1.58 1999/09/08 04:05:30 steve Exp $"
#endif
# include <cassert>
@ -370,13 +370,6 @@ NetAssign_::~NetAssign_()
NetAssign::NetAssign(const string&n, Design*des, unsigned w, NetExpr*rv)
: NetAssign_(n, w), rval_(rv)
{
bool flag = rval_->set_width(w);
if (flag == false) {
cerr << rv->get_line() << ": Expression bit width of " <<
rv->expr_width() << " conflicts with l-value bit width of "
<< w << "." << endl;
des->errors += 1;
}
}
NetAssign::~NetAssign()
@ -1754,6 +1747,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
/*
* $Log: netlist.cc,v $
* Revision 1.58 1999/09/08 04:05:30 steve
* Allow assign to not match rvalue width.
*
* Revision 1.57 1999/09/04 01:57:15 steve
* Generate fake adder code in vvm.
*

9
netlist.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: netlist.h,v 1.60 1999/09/03 04:28:38 steve Exp $"
#ident "$Id: netlist.h,v 1.61 1999/09/08 04:05:30 steve Exp $"
#endif
/*
@ -601,6 +601,10 @@ class NetProc {
* lvalue object and represents the elaborated lvalue. Thus, this
* appears as a procedural statement AND a structural node. The
* LineInfo is the location of the assignment statement in the source.
*
* NOTE: The elaborator will make an effort to match the width of the
* r-value to the with of the assign node, but targets and functions
* should know that this is not a guarantee.
*/
class NetAssign_ : public NetProc, public NetNode, public LineInfo {
@ -1548,6 +1552,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/*
* $Log: netlist.h,v $
* Revision 1.61 1999/09/08 04:05:30 steve
* Allow assign to not match rvalue width.
*
* Revision 1.60 1999/09/03 04:28:38 steve
* elaborate the binary plus operator.
*