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Spelling patch (Larry Doolittle)

This commit is contained in:
steve 2002-06-11 03:34:33 +00:00
parent 96b6eb6b30
commit d6c946f390
4 changed files with 44 additions and 35 deletions
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15
ieee1364-notes.txt
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@ -86,7 +86,7 @@ tool so it is not clear that the standard really is at fault. It is
clear, however, that somebody goofed somewhere. clear, however, that somebody goofed somewhere.
My personal opinion is that there is no logical need to require that My personal opinion is that there is no logical need to require that
all module_item_declarations preceed any other module items. I all module_item_declarations precede any other module items. I
personally would oppose such a restriction. It may make sense to personally would oppose such a restriction. It may make sense to
require that declarations of variables within a module be preceded by require that declarations of variables within a module be preceded by
their use, although even that is not necessary for the implementation their use, although even that is not necessary for the implementation
@ -97,7 +97,7 @@ sample2 can have implications that affect any declaration order
rules. When reaching into a module with a hierarchical name, the rules. When reaching into a module with a hierarchical name, the
module being referenced is already completely declared (or not module being referenced is already completely declared (or not
declared at all, as in sample2) so module_item order is completely declared at all, as in sample2) so module_item order is completely
irrelevent. But a "declare before use" rule would infect module irrelevant. But a "declare before use" rule would infect module
ordering, by requiring that modules that are used be first defined. ordering, by requiring that modules that are used be first defined.
@ -141,7 +141,7 @@ ports.
With the above in mind, I have decided to *allow* function and task With the above in mind, I have decided to *allow* function and task
ports to be declared with types, as long as the types are variable ports to be declared with types, as long as the types are variable
types, such ag reg or integer. Without this, there would be no types, such as reg or integer. Without this, there would be no
portable way to pass integers into functions/tasks. The standard does portable way to pass integers into functions/tasks. The standard does
not say it is allowed, but it doesn't *disallow* it, and other not say it is allowed, but it doesn't *disallow* it, and other
commercial tools seem to work similarly. commercial tools seem to work similarly.
@ -172,7 +172,7 @@ take it that x is allowed, as that is what Verilog-XL does.
There seems to be ambiguity in how code like this should be parsed: There seems to be ambiguity in how code like this should be parsed:
repeat (5) @(posedge clk) <statment>; repeat (5) @(posedge clk) <statement>;
There are two valid interpretations of this code, from the There are two valid interpretations of this code, from the
IEEE1364-1995 standard. One looks like this: IEEE1364-1995 standard. One looks like this:
@ -386,7 +386,7 @@ changes in inputs until the thread that changed the inputs yields
execution. execution.
* BIT AND PART SELECTS OF PARAMTERS * BIT AND PART SELECTS OF PARAMETERS
Bit and part selects are supposed to only be supported on vector nets Bit and part selects are supposed to only be supported on vector nets
and variables (wires, regs, etc.) However, it is common for Verilog and variables (wires, regs, etc.) However, it is common for Verilog
@ -400,8 +400,11 @@ constant vector of bits foo[X:0]. That is, zero based. The bit and
part selects operate from that assumption. part selects operate from that assumption.
$Id: ieee1364-notes.txt,v 1.11 2002/04/27 02:38:04 steve Exp $ $Id: ieee1364-notes.txt,v 1.12 2002/06/11 03:34:33 steve Exp $
$Log: ieee1364-notes.txt,v $ $Log: ieee1364-notes.txt,v $
Revision 1.12 2002/06/11 03:34:33 steve
Spelling patch (Larry Doolittle)
Revision 1.11 2002/04/27 02:38:04 steve Revision 1.11 2002/04/27 02:38:04 steve
Support selecting bits from parameters. Support selecting bits from parameters.

31
ivl_target.h
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: ivl_target.h,v 1.98 2002/05/27 00:08:45 steve Exp $" #ident "$Id: ivl_target.h,v 1.99 2002/06/11 03:34:33 steve Exp $"
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
@ -98,7 +98,7 @@ _BEGIN_DECL
* ivl_process_t * ivl_process_t
* A Verilog process is represented by one of these. A process may * A Verilog process is represented by one of these. A process may
* be an "initial" or an "always" process. These come from initial * be an "initial" or an "always" process. These come from initial
* or always statements from the verilog source. * or always statements from the Verilog source.
* *
* ivl_scope_t * ivl_scope_t
* Elaborated scopes within a design are represented by this * Elaborated scopes within a design are represented by this
@ -337,7 +337,7 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
* *
* ivl_design_process * ivl_design_process
* This function scans the processes (threads) in the design. It * This function scans the processes (threads) in the design. It
* calls the user suplied function on each of the processes until * calls the user supplied function on each of the processes until
* one of the functors returns non-0 or all the processes are * one of the functors returns non-0 or all the processes are
* scanned. This function will return 0, or the non-zero value that * scanned. This function will return 0, or the non-zero value that
* was returned from the last scanned process. * was returned from the last scanned process.
@ -515,7 +515,7 @@ extern unsigned ivl_logic_pins(ivl_net_logic_t net);
extern ivl_udp_t ivl_logic_udp(ivl_net_logic_t net); extern ivl_udp_t ivl_logic_udp(ivl_net_logic_t net);
extern unsigned ivl_logic_delay(ivl_net_logic_t net, unsigned transition); extern unsigned ivl_logic_delay(ivl_net_logic_t net, unsigned transition);
/* DEPRICATED */ /* DEPRECATED */
extern const char* ivl_logic_attr(ivl_net_logic_t net, const char*key); extern const char* ivl_logic_attr(ivl_net_logic_t net, const char*key);
extern unsigned ivl_logic_attr_cnt(ivl_net_logic_t net); extern unsigned ivl_logic_attr_cnt(ivl_net_logic_t net);
@ -550,7 +550,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* this device. * this device.
* *
* ivl_lpm_type * ivl_lpm_type
* Return the ivl_lpm_type_t of the secific LPM device. * Return the ivl_lpm_type_t of the specific LPM device.
* *
* ivl_lpm_width * ivl_lpm_width
* Return the width of the LPM device. What this means depends on * Return the width of the LPM device. What this means depends on
@ -567,7 +567,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* vector for devices that have more inputs. * vector for devices that have more inputs.
* *
* ivl_lpm_datab * ivl_lpm_datab
* Return the input data nexis for device types that have a second * Return the input data nexus for device types that have a second
* input vector. For example, arithmetic devices are like this. * input vector. For example, arithmetic devices are like this.
* *
* ivl_lpm_q * ivl_lpm_q
@ -580,7 +580,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* *
* ivl_lpm_size * ivl_lpm_size
* In addition to a width, some devices have a size. The size is * In addition to a width, some devices have a size. The size is
* often the number of inputs per out, i.e. the number of inputs * often the number of inputs per out, i.e., the number of inputs
* per bit for a MUX. * per bit for a MUX.
*/ */
extern const char* ivl_lpm_name(ivl_lpm_t net); extern const char* ivl_lpm_name(ivl_lpm_t net);
@ -705,7 +705,7 @@ extern ivl_signal_t ivl_lval_sig(ivl_lval_t net);
* connected to the nexus. * connected to the nexus.
* *
* If the target is an LPM device, then this value is zero, and it * If the target is an LPM device, then this value is zero, and it
* is up to the application to find the pin that referse to this * is up to the application to find the pin that refers to this
* nexus. The problem is that LPM devices do not have a pinout per * nexus. The problem is that LPM devices do not have a pinout per
* se, the pins all have specific names. * se, the pins all have specific names.
* *
@ -805,7 +805,7 @@ extern ivl_signal_t ivl_nexus_ptr_sig(ivl_nexus_ptr_t net);
* *
* ivl_scope_lpm * ivl_scope_lpm
* ivl_scope_lpms * ivl_scope_lpms
* Scopes have 0 or more LPM devices in them. These functions acess * Scopes have 0 or more LPM devices in them. These functions access
* those devices. * those devices.
* *
* ivl_scope_name * ivl_scope_name
@ -868,7 +868,7 @@ extern const char* ivl_scope_tname(ivl_scope_t net);
/* SIGNALS /* SIGNALS
* Signals are named things in the Verilog source, like wires and * Signals are named things in the Verilog source, like wires and
* regs, and also named things that are preated as temporaries during * regs, and also named things that are created as temporaries during
* certain elaboration or optimization steps. A signal may also be a * certain elaboration or optimization steps. A signal may also be a
* port of a module or task. * port of a module or task.
* *
@ -878,7 +878,7 @@ extern const char* ivl_scope_tname(ivl_scope_t net);
* ivl_signal_pins * ivl_signal_pins
* ivl_signal_pin * ivl_signal_pin
* The ivl_signal_pin function returns the nexus connected to the * The ivl_signal_pin function returns the nexus connected to the
* signal. If the signal is a vectory, the idx can be a non-zero * signal. If the signal is a vector, the idx can be a non-zero
* value, and the result is the nexus for the specified bit. * value, and the result is the nexus for the specified bit.
* *
* ivl_signal_port * ivl_signal_port
@ -892,7 +892,7 @@ extern const char* ivl_scope_tname(ivl_scope_t net);
* signal is signed. * signal is signed.
* *
* ivl_signal_type * ivl_signal_type
* Return the type of the signal, i.e. reg, wire, tri0, et al. * Return the type of the signal, i.e., reg, wire, tri0, etc.
* *
* ivl_signal_name * ivl_signal_name
* This function returns the fully scoped hierarchical name for the * This function returns the fully scoped hierarchical name for the
@ -929,7 +929,7 @@ extern ivl_attribute_t ivl_signal_attr_val(ivl_signal_t net, unsigned idx);
* may be a compound statement.) * may be a compound statement.)
* *
* The ivl_process_type function gets the type of the process, * The ivl_process_type function gets the type of the process,
* an "inital" or "always" statement. * an "initial" or "always" statement.
* *
* A process is placed in a scope. The statement within the process * A process is placed in a scope. The statement within the process
* operates within the scope of the process unless there are calls * operates within the scope of the process unless there are calls
@ -958,7 +958,7 @@ extern ivl_attribute_t ivl_process_attr_val(ivl_process_t net, unsigned idx);
* *
* The ivl_statement_type() function returns the type code for the * The ivl_statement_type() function returns the type code for the
* statement. This is the major type, and implies which of the later * statement. This is the major type, and implies which of the later
* functions are applicable to the statemnt. * functions are applicable to the statement.
*/ */
extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net); extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net);
@ -1050,6 +1050,9 @@ _END_DECL
/* /*
* $Log: ivl_target.h,v $ * $Log: ivl_target.h,v $
* Revision 1.99 2002/06/11 03:34:33 steve
* Spelling patch (Larry Doolittle)
*
* Revision 1.98 2002/05/27 00:08:45 steve * Revision 1.98 2002/05/27 00:08:45 steve
* Support carrying the scope of named begin-end * Support carrying the scope of named begin-end
* blocks down to the code generator, and have * blocks down to the code generator, and have

7
ivl_target.txt
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@ -2,7 +2,7 @@
Icarus Verilog LOADABLE TARGET API (ivl_target) Icarus Verilog LOADABLE TARGET API (ivl_target)
Copyright 2002 Stephen Williams <steve@icarus.com> Copyright 2002 Stephen Williams <steve@icarus.com>
$Id: ivl_target.txt,v 1.2 2002/03/17 19:31:17 steve Exp $ $Id: ivl_target.txt,v 1.3 2002/06/11 03:34:33 steve Exp $
The ivl_target API is the interface available to modules that the The ivl_target API is the interface available to modules that the
@ -12,7 +12,7 @@ for code generators that are intended to write netlist files or
executable programs. executable programs.
The functions and types of the API are summarized in the ivl_target.h The functions and types of the API are summarized in the ivl_target.h
header file. This ducument describes how the functions and types of header file. This document describes how the functions and types of
the API are used to access and interpret the netlist of the design. the API are used to access and interpret the netlist of the design.
@ -40,6 +40,9 @@ There are ivl_lpm_size() input ports, each with the width
ivl_lpm_data2_width(). The actual nexus is indexed by ivl_lpm_data2(). ivl_lpm_data2_width(). The actual nexus is indexed by ivl_lpm_data2().
$Log: ivl_target.txt,v $ $Log: ivl_target.txt,v $
Revision 1.3 2002/06/11 03:34:33 steve
Spelling patch (Larry Doolittle)
Revision 1.2 2002/03/17 19:31:17 steve Revision 1.2 2002/03/17 19:31:17 steve
Add API to support user defined function. Add API to support user defined function.

26
parse.y
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: parse.y,v 1.154 2002/05/26 01:39:02 steve Exp $" #ident "$Id: parse.y,v 1.155 2002/06/11 03:34:33 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -241,7 +241,7 @@ attribute
| IDENTIFIER '=' expression | IDENTIFIER '=' expression
{ PExpr*tmp = $3; { PExpr*tmp = $3;
if (!pform_expression_is_constant(tmp)) { if (!pform_expression_is_constant(tmp)) {
yyerror(@3, "error: attibute value " yyerror(@3, "error: attribute value "
"expression must be constant."); "expression must be constant.");
delete tmp; delete tmp;
tmp = 0; tmp = 0;
@ -285,7 +285,7 @@ block_item_decl
} }
| K_realtime list_of_identifiers ';' | K_realtime list_of_identifiers ';'
{ delete $2; { delete $2;
yyerror(@1, "sorry: reatime variables not supported."); yyerror(@1, "sorry: realtime variables not supported.");
} }
| K_parameter parameter_assign_list ';' | K_parameter parameter_assign_list ';'
| K_localparam localparam_assign_list ';' | K_localparam localparam_assign_list ';'
@ -1122,16 +1122,16 @@ list_of_identifiers
/* The list_of_ports and list_of_port_declarations rules are the /* The list_of_ports and list_of_port_declarations rules are the
port list formats for module ports. The lost_of_ports_opt rule is port list formats for module ports. The list_of_ports_opt rule is
only used by the module start rule. only used by the module start rule.
The first, the list_of_ports, is the 1364-1995 format, a list of The first, the list_of_ports, is the 1364-1995 format, a list of
port names, including .name() syntax. port names, including .name() syntax.
The list_of_port_declaractions the 1364-2001 format, an in-line The list_of_port_declarations the 1364-2001 format, an in-line
declaration of the ports. declaration of the ports.
In both cases, the lost_of_ports and lost_of_port_declarations In both cases, the list_of_ports and list_of_port_declarations
returns an array of Module::port_t* items that include the name returns an array of Module::port_t* items that include the name
of the port internally and externally. The actual creation of the of the port internally and externally. The actual creation of the
nets/variables is done in the declaration, whether internal to nets/variables is done in the declaration, whether internal to
@ -1319,7 +1319,7 @@ assign_list
/* This is the global structure of a module. A module in a start /* This is the global structure of a module. A module in a start
section, with optional ports, then an opetional list of module section, with optional ports, then an optional list of module
items, and finally an end marker. */ items, and finally an end marker. */
module : module_start IDENTIFIER module : module_start IDENTIFIER
@ -1539,7 +1539,7 @@ module_item
yyerrok; yyerrok;
} }
/* These rules are for the Icarus VErilog specific $attribute /* These rules are for the Icarus Verilog specific $attribute
extensions. Then catch the parameters of the $attribute keyword. */ extensions. Then catch the parameters of the $attribute keyword. */
| KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')' ';' | KK_attribute '(' IDENTIFIER ',' STRING ',' STRING ')' ';'
@ -1548,7 +1548,7 @@ module_item
delete $5; delete $5;
} }
| KK_attribute '(' error ')' ';' | KK_attribute '(' error ')' ';'
{ yyerror(@1, "error: Misformed $attribute parameter list."); } { yyerror(@1, "error: Malformed $attribute parameter list."); }
; ;
@ -1635,8 +1635,8 @@ parameter_assign_list
; ;
/* Localparam assignments and asignment lists are broken into /* Localparam assignments and assignment lists are broken into
separate BNF so that I can call slightly different paramter separate BNF so that I can call slightly different parameter
handling code. They parse the same as parameters, they just handling code. They parse the same as parameters, they just
behave differently when someone tries to override them. */ behave differently when someone tries to override them. */
@ -1784,7 +1784,7 @@ port
$$ = tmp; $$ = tmp;
} }
/* This attaches a name to a port reference contatenation list so /* This attaches a name to a port reference concatenation list so
that parameter passing be name is possible. */ that parameter passing be name is possible. */
| '.' IDENTIFIER '(' '{' port_reference_list '}' ')' | '.' IDENTIFIER '(' '{' port_reference_list '}' ')'
@ -2373,7 +2373,7 @@ statement
| K_for '(' lpvalue '=' expression ';' expression ';' | K_for '(' lpvalue '=' expression ';' expression ';'
error ')' statement error ')' statement
{ $$ = 0; { $$ = 0;
yyerror(@9, "error: Error in for loop step assigment."); yyerror(@9, "error: Error in for loop step assignment.");
} }
| K_for '(' lpvalue '=' expression ';' error ';' | K_for '(' lpvalue '=' expression ';' error ';'
lpvalue '=' expression ')' statement lpvalue '=' expression ')' statement