luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Avoid seg fault when the range for a module/gate is empty

This commit is contained in:
Cary R 2024-12-28 17:15:07 -08:00
parent 47cf3707fc
commit d484cb63d6
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
pform_dump.cc
View File

@ -718,6 +718,7 @@ void PGate::dump_delays(ostream&out) const
void PGate::dump_ranges(ostream&out) const void PGate::dump_ranges(ostream&out) const
{ {
if (ranges_ == 0) return;
for (list<pform_range_t>::iterator cur = ranges_->begin() for (list<pform_range_t>::iterator cur = ranges_->begin()
; cur != ranges_->end() ; ++cur) { ; cur != ranges_->end() ; ++cur) {
out << "["; out << "[";
@ -1681,7 +1682,7 @@ void Module::dump_specparams_(ostream&out, unsigned indent) const
void Module::dump_timingchecks_(ostream&out, unsigned indent) const void Module::dump_timingchecks_(ostream&out, unsigned indent) const
{ {
cout << "dump_timingchecks_" << endl; out << " PFORM DUMP TIMINGCHECKS" << endl;
for (const auto cur : timing_checks) { for (const auto cur : timing_checks) {
cur->dump(out, indent); cur->dump(out, indent);