Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl

2008-08-21 18:35:54 +01:00 · 2008-08-21 18:35:54 +01:00 · d3b7d7a13d
parent 4ebe09bb72 b92b62a8fb
commit d3b7d7a13d
4 changed files with 4 additions and 0 deletions
--- a/PExpr.cc
+++ b/PExpr.cc
@ -20,6 +20,7 @@
 # include "config.h"

 # include  <iostream>
+# include  <cstring>

 # include  "PExpr.h"
 # include  "Module.h"
--- a/elab_pexpr.cc
+++ b/elab_pexpr.cc
@ -25,6 +25,7 @@
 # include  "netmisc.h"

 # include  <cstdlib>
+# include  <cstring>
 # include  <iostream>
 # include  "ivl_assert.h"

--- a/eval_tree.cc
+++ b/eval_tree.cc
@ -22,6 +22,7 @@

 # include  <iostream>
 # include  <cstdlib>
+# include  <cstring>
 # include  <math.h>

 # include  "netlist.h"
--- a/vvp/vvp.def
+++ b/vvp/vvp.def
@ -37,3 +37,4 @@ vpi_vprintf

 vpip_format_strength
 vpip_set_return_value
+vpip_calc_clog2