Initial BLIF code generator.
Add the -tblif code generator target, and include some basic useful behavior.
This commit is contained in:
Stephen Williams
parent
c4edbda969
commit
d2034a6458
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@ -51,6 +51,8 @@ dep
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*.vpi
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/cadpli/cadpli.vpl
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/tgt-blif/Makefile
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# lex, yacc and gperf output
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/driver/cflexor.c
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/driver/cfparse.c
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@ -38,7 +38,7 @@ srcdir = @srcdir@
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datarootdir = @datarootdir@
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SUBDIRS = ivlpp vhdlpp vvp vpi libveriuser cadpli tgt-null tgt-stub tgt-vvp \
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tgt-vhdl tgt-vlog95 tgt-pcb driver
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tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif driver
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# Only run distclean for these directories.
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NOTUSED = tgt-fpga tgt-pal tgt-verilog
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@ -325,4 +325,4 @@ AC_MSG_ERROR(cannot configure white space in libdir: $libdir)
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fi
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AC_MSG_RESULT(ok)
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AC_OUTPUT(Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile)
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AC_OUTPUT(Makefile ivlpp/Makefile vhdlpp/Makefile vvp/Makefile vpi/Makefile driver/Makefile driver-vpi/Makefile cadpli/Makefile libveriuser/Makefile tgt-null/Makefile tgt-stub/Makefile tgt-vvp/Makefile tgt-vhdl/Makefile tgt-fpga/Makefile tgt-verilog/Makefile tgt-pal/Makefile tgt-vlog95/Makefile tgt-pcb/Makefile tgt-blif/Makefile)
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@ -0,0 +1,104 @@
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#
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# This source code is free software; you can redistribute it
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# and/or modify it in source code form under the terms of the GNU
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# Library General Public License as published by the Free Software
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# Foundation; either version 2 of the License, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU Library General Public License for more details.
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#
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# You should have received a copy of the GNU Library General Public
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# License along with this program; if not, write to the Free
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# Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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# Boston, MA 02110-1301, USA.
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#
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SHELL = /bin/sh
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suffix = @install_suffix@
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prefix = @prefix@
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exec_prefix = @exec_prefix@
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srcdir = @srcdir@
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VPATH = $(srcdir)
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bindir = @bindir@
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libdir = @libdir@
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CC = @CC@
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CC = @CXX@
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INSTALL = @INSTALL@
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INSTALL_PROGRAM = @INSTALL_PROGRAM@
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INSTALL_DATA = @INSTALL_DATA@
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ifeq (@srcdir@,.)
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INCLUDE_PATH = -I. -I..
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else
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INCLUDE_PATH = -I. -I.. -I$(srcdir) -I$(srcdir)/..
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endif
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CPPFLAGS = $(INCLUDE_PATH) @CPPFLAGS@ @DEFS@ @PICFLAG@
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CXXFLAGS = @WARNING_FLAGS@ @CXXFLAGS@
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LDFLAGS = @LDFLAGS@
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O = blif.o nex_data.o
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all: dep blif.tgt
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check: all
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clean:
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rm -rf *.o dep blif.tgt
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distclean: clean
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rm -f Makefile config.log
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cppcheck: $(O:.o=.c)
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cppcheck --enable=all -f $(INCLUDE_PATH) $^
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Makefile: $(srcdir)/Makefile.in ../config.status
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cd ..; ./config.status --file=tgt-blif/$@
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dep:
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mkdir dep
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%.o: %.cc
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$(CXX) $(CPPFLAGS) $(CXXFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
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mv $*.d dep
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ifeq (@WIN32@,yes)
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TGTLDFLAGS=-L.. -livl
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TGTDEPLIBS=../libivl.a
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else
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TGTLDFLAGS=
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TGTDEPLIBS=
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endif
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blif.tgt: $O $(TGTDEPLIBS)
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$(CC) @shared@ $(LDFLAGS) -o $@ $O $(TGTLDFLAGS)
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install: all installdirs $(libdir)/ivl$(suffix)/blif.tgt $(INSTALL_DOC) $(libdir)/ivl$(suffix)/blif.conf $(libdir)/ivl$(suffix)/blif-s.conf
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$(libdir)/ivl$(suffix)/blif.tgt: ./blif.tgt
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$(INSTALL_PROGRAM) ./blif.tgt "$(DESTDIR)$(libdir)/ivl$(suffix)/blif.tgt"
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$(libdir)/ivl$(suffix)/blif.conf: $(srcdir)/blif.conf
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$(INSTALL_DATA) $(srcdir)/blif.conf "$(DESTDIR)$(libdir)/ivl$(suffix)/blif.conf"
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$(libdir)/ivl$(suffix)/blif-s.conf: $(srcdir)/blif-s.conf
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$(INSTALL_DATA) $(srcdir)/blif-s.conf "$(DESTDIR)$(libdir)/ivl$(suffix)/blif-s.conf"
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installdirs: $(srcdir)/../mkinstalldirs
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$(srcdir)/../mkinstalldirs "$(DESTDIR)$(bindir)" "$(DESTDIR)$(libdir)/ivl$(suffix)"
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uninstall:
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rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/blif.tgt"
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rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/blif.conf"
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rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/blif-s.conf"
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-include $(patsubst %.o, dep/%.d, $O)
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@ -0,0 +1,6 @@
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functor:synth2
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functor:synth
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functor:syn-rules
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functor:cprop
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functor:nodangle
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flag:DLL=blif.tgt
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@ -0,0 +1,234 @@
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/*
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* Copyright (c) 2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "version_base.h"
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# include "version_tag.h"
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# include "config.h"
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# include "ivl_target.h"
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# include "nex_data.h"
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# include <vector>
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# include <cstdio>
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# include <cstring>
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# include <cassert>
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using namespace std;
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/*
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* This is a BLIF target module.
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*/
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static const char*version_string =
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"Icarus Verilog BLIF Code Generator " VERSION " (" VERSION_TAG ")\n\n"
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"Copyright (c) 2013 Stephen Williams (steve@icarus.com)\n\n"
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" This program is free software; you can redistribute it and/or modify\n"
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" it under the terms of the GNU General Public License as published by\n"
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" the Free Software Foundation; either version 2 of the License, or\n"
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" (at your option) any later version.\n"
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"\n"
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" This program is distributed in the hope that it will be useful,\n"
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" but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
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" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
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" GNU General Public License for more details.\n"
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"\n"
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" You should have received a copy of the GNU General Public License along\n"
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" with this program; if not, write to the Free Software Foundation, Inc.,\n"
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" 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n"
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;
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static int emit_blif(const char*blif_path, ivl_scope_t model);
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int target_design(ivl_design_t des)
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{
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int rc = 0;
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const char*blif_path = ivl_design_flag(des, "-o");
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// Locate the root scope for the design. Note that the BLIF
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// format implies that there is a single root of the model.
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ivl_scope_t*roots;
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unsigned nroots;
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ivl_design_roots(des, &roots, &nroots);
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if (nroots != 1) {
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fprintf(stderr, "BLIF: The BLIF code generator requires that there be only one root scope.\n");
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return 1;
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}
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assert(roots[0]);
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if (ivl_scope_type(roots[0]) != IVL_SCT_MODULE) {
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fprintf(stderr, "BLIF: The root scope %s must be a module.\n", ivl_scope_basename(roots[0]));
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return 1;
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}
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// Emit to the destination file.
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assert(blif_path);
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rc += emit_blif(blif_path, roots[0]);
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return rc;
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}
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const char* target_query(const char*key)
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{
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if (strcmp(key,"version") == 0)
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return version_string;
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return 0;
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}
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/*
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* Print all the bits of a signal. This is for the .input or .output
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* lines of a .model. All the bits need to be exploded, so print each
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* bit of a vector as its own name.
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*/
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static void print_signal_bits(FILE*fd, ivl_signal_t sig)
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{
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ivl_nexus_t nex = ivl_signal_nex(sig, 0);
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blif_nex_data_t* ned = blif_nex_data_t::get_nex_data(nex);
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ned->set_name(ivl_signal_basename(sig));
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if (ivl_signal_packed_dimensions(sig) == 0) {
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fprintf(fd, " %s", ivl_signal_basename(sig));
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return;
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}
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assert(ivl_signal_packed_dimensions(sig) == 1);
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int msb = ivl_signal_packed_msb(sig,0);
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int lsb = ivl_signal_packed_lsb(sig,0);
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if (msb < lsb) {
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int tmp = msb;
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msb = lsb;
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lsb = tmp;
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}
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for (int idx = msb ; idx >= lsb ; idx -= 1) {
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fprintf(fd, " %s[%d]", ivl_signal_basename(sig), idx);
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}
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}
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static void print_logic_gate(FILE*fd, ivl_net_logic_t net)
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{
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#if 0
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fprintf(fd, "# LOGIC: name=%s, type=%d, pins=%u, width=%u\n",
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ivl_logic_basename(net), ivl_logic_type(net),
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ivl_logic_pins(net), ivl_logic_width(net));
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#endif
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fprintf(fd, ".names");
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ivl_nexus_t nex;
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blif_nex_data_t*ned;
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for (unsigned idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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nex = ivl_logic_pin(net,idx);
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ned = blif_nex_data_t::get_nex_data(nex);
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fprintf(fd, " %s", ned->get_name());
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}
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nex = ivl_logic_pin(net,0);
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ned = blif_nex_data_t::get_nex_data(nex);
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fprintf(fd, " %s", ned->get_name());
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fprintf(fd, "\n");
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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for (unsigned idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1)
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fprintf(fd, "1");
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fprintf(fd, " 1\n");
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break;
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case IVL_LO_OR:
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assert(ivl_logic_pins(net)==3);
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fprintf(fd, "1- 1\n");
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fprintf(fd, "-1 1\n");
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break;
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case IVL_LO_XOR:
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assert(ivl_logic_pins(net)==3);
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fprintf(fd, "10 1\n");
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fprintf(fd, "01 1\n");
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break;
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default:
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fprintf(fd, "# ERROR: Logic type not handled\n");
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break;
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}
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}
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static int emit_blif(const char*blif_path, ivl_scope_t model)
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{
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int rc = 0;
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FILE*fd = fopen(blif_path, "wt");
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if (fd == 0) {
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perror(blif_path);
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return 1;
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}
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fprintf(fd, ".model %s\n", ivl_scope_basename(model));
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// The root scope
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vector<ivl_signal_t> ports_in;
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vector<ivl_signal_t> ports_out;
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for (unsigned idx = 0 ; idx < ivl_scope_sigs(model) ; idx += 1) {
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ivl_signal_t prt = ivl_scope_sig(model, idx);
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ivl_signal_port_t dir = ivl_signal_port(prt);
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switch (dir) {
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case IVL_SIP_NONE:
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break;
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case IVL_SIP_INPUT:
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ports_in.push_back(prt);
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break;
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case IVL_SIP_OUTPUT:
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ports_out.push_back(prt);
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break;
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case IVL_SIP_INOUT:
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fprintf(stderr, "BLIF: error: "
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"Model port %s is bi-directional.\n",
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ivl_signal_basename(prt));
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rc += 1;
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ports_in.push_back(prt);
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ports_out.push_back(prt);
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break;
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}
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}
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if (ports_in.size() > 0) {
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fprintf(fd, ".inputs");
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for (size_t idx = 0 ; idx < ports_in.size() ; idx += 1) {
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ivl_signal_t prt = ports_in[idx];
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print_signal_bits(fd, prt);
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}
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fprintf(fd, "\n");
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}
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if (ports_out.size() > 0) {
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fprintf(fd, ".outputs");
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for (size_t idx = 0 ; idx < ports_out.size() ; idx += 1) {
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ivl_signal_t prt = ports_out[idx];
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print_signal_bits(fd, prt);
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}
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fprintf(fd, "\n");
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}
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for (unsigned idx = 0 ; idx < ivl_scope_logs(model) ; idx += 1) {
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ivl_net_logic_t net = ivl_scope_log(model, idx);
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assert(net);
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print_logic_gate(fd, net);
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}
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fprintf(fd, ".end\n");
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fclose(fd);
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return rc;
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}
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@ -0,0 +1,3 @@
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functor:cprop
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functor:nodangle
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flag:DLL=blif.tgt
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@ -0,0 +1,74 @@
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/*
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* Copyright (c) 2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "nex_data.h"
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# include <cstdlib>
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# include <cstdio>
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# include <cstring>
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# include <cassert>
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inline blif_nex_data_t::blif_nex_data_t(ivl_nexus_t nex)
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: nex_(nex), name_(0)
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{
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}
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blif_nex_data_t::~blif_nex_data_t()
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{
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if (name_) free(name_);
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}
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blif_nex_data_t* blif_nex_data_t::get_nex_data(ivl_nexus_t nex)
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{
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void*tmp = ivl_nexus_get_private(nex);
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if (tmp != 0) return reinterpret_cast<blif_nex_data_t*> (tmp);
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blif_nex_data_t*data = new blif_nex_data_t(nex);
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ivl_nexus_set_private(nex, data);
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return data;
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}
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void blif_nex_data_t::set_name(const char*txt)
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{
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assert(name_ == 0);
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name_ = strdup(txt);
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}
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const char* blif_nex_data_t::get_name(void)
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{
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if (name_) return name_;
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for (unsigned idx = 0 ; idx < ivl_nexus_ptrs(nex_) ; idx += 1) {
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ivl_nexus_ptr_t ptr = ivl_nexus_ptr(nex_, idx);
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ivl_signal_t sig = ivl_nexus_ptr_sig(ptr);
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if (sig == 0)
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continue;
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name_ = strdup(ivl_signal_basename(sig));
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break;
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}
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if (name_ == 0) {
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char buf[64];
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snprintf(buf, sizeof buf, "@%p", nex_);
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name_ = strdup(buf);
|
||||
}
|
||||
|
||||
assert(name_);
|
||||
return name_;
|
||||
}
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
#ifndef __nex_data_H
|
||||
#define __nex_data_H
|
||||
/*
|
||||
* Copyright (c) 2013 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "ivl_target.h"
|
||||
|
||||
/*
|
||||
* The ivl_target.h API allows for binding data to a nexus. This class
|
||||
* represents the data that we want to attach to a nexus.
|
||||
*/
|
||||
class blif_nex_data_t {
|
||||
|
||||
private:
|
||||
// The constructors are private. Only the get_nex_data()
|
||||
// function can create these objects.
|
||||
blif_nex_data_t(ivl_nexus_t nex);
|
||||
~blif_nex_data_t();
|
||||
|
||||
public:
|
||||
// Return the blif_nex_data_t object that is associated with
|
||||
// the given nexus. If the nexus does not have a nex_data_t
|
||||
// object, then create it and bind it to the nexus. Thus, this
|
||||
// function will always return the same nex_data instance for
|
||||
// the same nexus.
|
||||
static blif_nex_data_t* get_nex_data(ivl_nexus_t nex);
|
||||
|
||||
void set_name(const char*);
|
||||
|
||||
// Get the symbolic name chosen for this nexus.
|
||||
const char*get_name(void);
|
||||
|
||||
public:
|
||||
ivl_nexus_t nex_;
|
||||
char*name_;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue