Debug text.
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synth2.cc
19
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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*/
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#ifdef HAVE_CVS_IDENT
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.43 2005/04/25 01:35:58 steve Exp $"
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#ident "$Id: synth2.cc,v 1.44 2005/05/15 04:45:50 steve Exp $"
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#endif
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#endif
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# include "config.h"
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# include "config.h"
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@ -87,6 +87,12 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope,
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}
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}
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assert(lval_->more == 0);
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assert(lval_->more == 0);
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if (debug_synth2) {
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cerr << get_line() << ": debug: l-value signal is "
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<< lsig->vector_width() << " bits, r-value signal is "
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<< rsig->vector_width() << " bits." << endl;
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}
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#if 0
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#if 0
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/* The l-value and r-value map must have the same width. */
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/* The l-value and r-value map must have the same width. */
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if (lval_->lwidth() != nex_map->vector_width()) {
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if (lval_->lwidth() != nex_map->vector_width()) {
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@ -894,6 +900,14 @@ bool NetProcTop::synth_sync(Design*des)
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/* Make a model FF that will connect to the first item in the
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/* Make a model FF that will connect to the first item in the
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set, and will also take the initial connection of clocks
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set, and will also take the initial connection of clocks
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and resets. */
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and resets. */
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if (debug_synth2) {
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cerr << get_line() << ": debug: "
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<< "Top level making a "
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<< nex_set[0]->vector_width() << "-wide "
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<< "NetFF device." << endl;
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}
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NetFF*ff = new NetFF(scope(), scope()->local_symbol(),
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NetFF*ff = new NetFF(scope(), scope()->local_symbol(),
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nex_set[0]->vector_width());
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nex_set[0]->vector_width());
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des->add_node(ff);
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des->add_node(ff);
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@ -1036,6 +1050,9 @@ void synth2(Design*des)
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/*
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/*
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* $Log: synth2.cc,v $
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* $Log: synth2.cc,v $
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* Revision 1.44 2005/05/15 04:45:50 steve
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* Debug text.
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*
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* Revision 1.43 2005/04/25 01:35:58 steve
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* Revision 1.43 2005/04/25 01:35:58 steve
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* Reimplement basic asynchronous processes.
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* Reimplement basic asynchronous processes.
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*
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*
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