luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Get bits of odd sized hex representation.

This commit is contained in:
steve 1999-07-17 18:25:38 +00:00
parent 772f38ca1e
commit cfb27a1fc4
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lexor.lex
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: lexor.lex,v 1.32 1999/07/11 17:15:16 steve Exp $" #ident "$Id: lexor.lex,v 1.33 1999/07/17 18:25:38 steve Exp $"
#endif #endif
//# define YYSTYPE lexval //# define YYSTYPE lexval
@ -651,12 +651,12 @@ static verinum*make_sized_hex(const char*txt)
while (*ptr && ((*ptr == ' ') || (*ptr == '\t'))) while (*ptr && ((*ptr == ' ') || (*ptr == '\t')))
ptr += 1; ptr += 1;
verinum::V*bits = new verinum::V[size]; verinum::V*bits = new verinum::V[(size+3)&~3];
unsigned idx = 0; unsigned idx = 0;
char*eptr = ptr + strlen(ptr) - 1; char*eptr = ptr + strlen(ptr) - 1;
while ((eptr >= ptr) && (idx <= (size-4))) { while ((eptr >= ptr) && (idx < size)) {
switch (*eptr) { switch (*eptr) {
case 'x': case 'X': case 'x': case 'X':
bits[idx++] = verinum::Vx; bits[idx++] = verinum::Vx;