Support time0 resolution of combinational threads.
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steve
parent
aa40930278
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cee34f8a8a
12
README.txt
12
README.txt
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@ -423,6 +423,16 @@ language that are defined.
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where one wants to iterate over all the objects in a scope
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without iterating over all the contained types explicitly.
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time 0 race resolution.
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Combinational logic is routinely modeled using always
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blocks. However, this can lead to race conditions if the
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inputs to the combinational block are initialized in initial
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statements. Icarus Verilog slightly modifies time 0 scheduling
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by arranging for always statements with ANYEDGE sensitivity
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lists to be scheduled before any other threads. This causes
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combinational always blocks to be triggered when the values in
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the sensitivity list are initialzed by initial threads.
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6.0 CREDITS
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@ -445,7 +455,7 @@ removed from the list) send e-mail to me.
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FreeBSD/{Intel,alpha}
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Ying-Chieh Liao <ijliao@FreeBSD.org>
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Linux/{alpha,Intel} (RPMS)
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Linux/{alpha,AMD64,Intel} (RPMS)
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Stephen Williams <steve@icarus.com>
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Linux/* (.debs)
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10
async.cc
10
async.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: async.cc,v 1.4 2002/08/18 22:07:16 steve Exp $"
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#ident "$Id: async.cc,v 1.5 2003/09/04 20:28:05 steve Exp $"
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#endif
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# include "config.h"
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@ -39,8 +39,9 @@ bool NetCondit::is_asynchronous()
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bool NetEvWait::is_asynchronous()
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{
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/* The "sense" set contains the set of Nexa that are in the
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sensitivity list. We also presume here that the list is
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only LEVEL sensitive. */
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sensitivity list. We also require that the events are all
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level sensitive, but the nex_async_ method takes care of
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that test. */
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NexusSet*sense = new NexusSet;
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for (unsigned idx = 0 ; idx < nevents_ ; idx += 1) {
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NexusSet*tmp = event(idx)->nex_async_();
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@ -81,6 +82,9 @@ bool NetProcTop::is_asynchronous()
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/*
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* $Log: async.cc,v $
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* Revision 1.5 2003/09/04 20:28:05 steve
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* Support time0 resolution of combinational threads.
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*
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* Revision 1.4 2002/08/18 22:07:16 steve
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* Detect temporaries in sequential block synthesis.
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*
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@ -1,4 +1,13 @@
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ATTRIBUTE NAMING CONVENTIONS
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Attributes that are specific to Icarus Verilog, and are intended to be
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of use to programmers, start with the prefix "ivl_".
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Attributes with the "_ivl_" prefix are set aside for internal
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use. They may be generated internally by the compiler. They need not
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be documented here.
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ATTRIBUTES TO CONTROL SYNTHESIS
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The following is a summary of Verilog attributes that Icarus Verilog
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@ -62,3 +71,15 @@ warning.)
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* Other Attributes
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[ none defined yet ]
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MISC
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(* _ivl_schedule_push *)
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If this attribute is attached to a thread object (always or
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initial statement) then the vvp code generator will generate code
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that causes the scheduler to push this thread at compile time. The
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compiler may internally add this attribute to always statements if
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it detects that it is combinational. This helps resolve time-0
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races.
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41
elaborate.cc
41
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elaborate.cc,v 1.286 2003/08/28 04:11:17 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.287 2003/09/04 20:28:05 steve Exp $"
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#endif
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# include "config.h"
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@ -2470,6 +2470,42 @@ bool Module::elaborate(Design*des, NetScope*scope) const
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top->set_line(*(*st));
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des->add_process(top);
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/* Detect the special case that this is a combinational
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always block. We want to attach an _ivl_schedule_push
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attribute to this process so that it starts up and
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gets into its wait statement before non-combinational
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code is executed. */
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do {
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if (top->type() != NetProcTop::KALWAYS)
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break;
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NetEvWait*st = dynamic_cast<NetEvWait*>(top->statement());
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if (st == 0)
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break;
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if (st->nevents() != 1)
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break;
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NetEvent*ev = st->event(0);
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if (ev->nprobe() == 0)
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break;
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bool anyedge_test = true;
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for (unsigned idx = 0 ; anyedge_test && (idx<ev->nprobe())
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; idx += 1) {
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const NetEvProbe*pr = ev->probe(idx);
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if (pr->edge() != NetEvProbe::ANYEDGE)
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anyedge_test = false;
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}
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if (! anyedge_test)
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break;
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top->attribute("_ivl_schedule_push", verinum(1));
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} while (0);
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}
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return result_flag;
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@ -2579,6 +2615,9 @@ Design* elaborate(list<const char*>roots)
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.287 2003/09/04 20:28:05 steve
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* Support time0 resolution of combinational threads.
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*
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* Revision 1.286 2003/08/28 04:11:17 steve
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* Spelling patch.
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*
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: vvp_process.c,v 1.88 2003/07/29 05:12:10 steve Exp $"
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#ident "$Id: vvp_process.c,v 1.89 2003/09/04 20:28:06 steve Exp $"
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#endif
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# include "vvp_priv.h"
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@ -1461,9 +1461,27 @@ static int show_statement(ivl_statement_t net, ivl_scope_t sscope)
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int draw_process(ivl_process_t net, void*x)
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{
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int rc = 0;
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unsigned idx;
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ivl_scope_t scope = ivl_process_scope(net);
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ivl_statement_t stmt = ivl_process_stmt(net);
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int push_flag = 0;
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for (idx = 0 ; idx < ivl_process_attr_cnt(net) ; idx += 1) {
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ivl_attribute_t attr = ivl_process_attr_val(net, idx);
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if (strcmp(attr->key, "_ivl_schedule_push") == 0) {
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push_flag = 1;
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} else if (strcmp(attr->key, "ivl_combinational") == 0) {
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push_flag = 1;
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}
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}
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local_count = 0;
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fprintf(vvp_out, " .scope S_%p;\n", scope);
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@ -1492,8 +1510,12 @@ int draw_process(ivl_process_t net, void*x)
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/* Now write out the .thread directive that tells vvp where
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the thread starts. */
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fprintf(vvp_out, " .thread T_%d;\n", thread_count);
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if (push_flag) {
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fprintf(vvp_out, " .thread T_%d, $push;\n", thread_count);
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} else {
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fprintf(vvp_out, " .thread T_%d;\n", thread_count);
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}
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thread_count += 1;
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return rc;
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@ -1535,6 +1557,9 @@ int draw_func_definition(ivl_scope_t scope)
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/*
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* $Log: vvp_process.c,v $
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* Revision 1.89 2003/09/04 20:28:06 steve
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* Support time0 resolution of combinational threads.
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*
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* Revision 1.88 2003/07/29 05:12:10 steve
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* All the threads of a named fork go into sub-scope.
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*
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@ -1555,132 +1580,5 @@ int draw_func_definition(ivl_scope_t scope)
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*
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* Revision 1.82 2003/03/06 01:17:46 steve
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* Use number for event labels.
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*
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* Revision 1.81 2003/02/28 20:21:13 steve
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* Merge vpi_call and vpi_func draw functions.
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*
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* Revision 1.80 2003/02/27 20:38:12 steve
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* Handle assign of real values to vectors.
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*
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* Revision 1.79 2003/02/03 01:09:20 steve
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* Allow $display of $simtime.
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*
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* Revision 1.78 2003/01/27 00:14:37 steve
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* Support in various contexts the $realtime
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* system task.
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*
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* Revision 1.77 2003/01/26 21:16:00 steve
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* Rework expression parsing and elaboration to
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* accommodate real/realtime values and expressions.
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*
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* Revision 1.76 2002/11/21 22:43:13 steve
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* %set/x0 instruction to support bounds checking.
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*
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* Revision 1.75 2002/11/17 18:31:09 steve
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* Generate unique labels for force functors.
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*
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* Revision 1.74 2002/11/08 05:00:31 steve
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* Use the vectorized %assign where appropriate.
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*
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* Revision 1.73 2002/11/07 05:19:55 steve
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* Use Vector %set to set constants in variables.
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*
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* Revision 1.72 2002/11/07 03:12:18 steve
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* Vectorize load from REG variables.
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*
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* Revision 1.71 2002/09/27 20:24:42 steve
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* Allow expression lookaside map to spam statements.
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*
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* Revision 1.70 2002/09/27 16:33:34 steve
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* Add thread expression lookaside map.
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*
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* Revision 1.69 2002/09/24 04:20:32 steve
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* Allow results in register bits 47 in certain cases.
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*
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* Revision 1.68 2002/09/13 03:12:50 steve
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* Optimize ==1 when in context where x vs z doesnt matter.
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*
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* Revision 1.67 2002/09/01 00:19:35 steve
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* Watch for x indices in l-value of non-blocking assignments.
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*
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* Revision 1.66 2002/08/31 03:48:50 steve
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* Fix reverse bit ordered bit select in continuous assignment.
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*
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* Revision 1.65 2002/08/27 05:39:57 steve
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* Fix l-value indexing of memories and vectors so that
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* an unknown (x) index causes so cell to be addresses.
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*
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* Fix tangling of label identifiers in the fork-join
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* code generator.
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*
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* Revision 1.64 2002/08/19 00:06:12 steve
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* Allow release to handle removal of target net.
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*
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* Revision 1.63 2002/08/12 01:35:04 steve
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* conditional ident string using autoconfig.
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*
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* Revision 1.62 2002/08/07 00:54:39 steve
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* Add force to nets.
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*
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* Revision 1.61 2002/08/04 18:28:15 steve
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* Do not use hierarchical names of memories to
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* generate vvp labels. -tdll target does not
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* used hierarchical name string to look up the
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* memory objects in the design.
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*
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* Revision 1.60 2002/08/03 22:30:48 steve
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* Eliminate use of ivl_signal_name for signal labels.
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*
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* Revision 1.59 2002/06/02 18:57:17 steve
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* Generate %cmpi/u where appropriate.
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*
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* Revision 1.58 2002/05/27 00:08:45 steve
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* Support carrying the scope of named begin-end
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* blocks down to the code generator, and have
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* the vvp code generator use that to support disable.
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*
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* Revision 1.57 2002/04/22 02:41:30 steve
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* Reduce the while loop expression if needed.
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*
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* Revision 1.56 2002/04/21 22:31:02 steve
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* Redo handling of assignment internal delays.
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* Leave it possible for them to be calculated
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* at run time.
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*
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* Revision 1.55 2002/04/14 19:19:21 steve
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* Handle empty true case of conditional statements.
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*
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* Revision 1.54 2002/04/14 03:54:40 steve
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* Vector constants to vpi_call can have sign.
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*
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* Revision 1.53 2002/04/14 02:56:19 steve
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* Support signed expressions through to VPI.
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*
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* Revision 1.52 2002/01/11 05:23:05 steve
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* Handle certain special cases of stime.
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*
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* Revision 1.51 2001/12/05 05:41:20 steve
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* Make sure fork labels are globally unique.
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*
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* Revision 1.50 2001/11/18 01:28:18 steve
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* Generate force code for variable l-values.
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*
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* Revision 1.49 2001/11/14 03:28:49 steve
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* DLL target support for force and release.
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*
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* Revision 1.48 2001/11/01 19:31:40 steve
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* make fork label into complete statemnt.
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*
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* Revision 1.47 2001/11/01 04:26:57 steve
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* Generate code for deassign and cassign.
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*
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* Revision 1.46 2001/10/19 23:52:36 steve
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* Add trailing ; to fork-join out labels.
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*
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* Revision 1.45 2001/09/15 18:27:04 steve
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* Make configure detect malloc.h
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*
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* Revision 1.44 2001/09/01 00:58:16 steve
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* dead comments.
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*/
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