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Spelling fixes

This commit is contained in:
Larry Doolittle 2015-08-16 18:20:47 -07:00 committed by Stephen Williams
parent a66361a4f2
commit cb73accd84
7 changed files with 7 additions and 7 deletions
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2
driver/iverilog.man.in
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@ -30,7 +30,7 @@ different set of programs. The path given is used to locate
\fIivlpp\fP, \fIivl\fP, code generators and the VPI modules. \fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
.TP 8 .TP 8
.B -c\fIfile\fP -f\fIfile\fP .B -c\fIfile\fP -f\fIfile\fP
These flags specifies an input file that contains a list of Verilog These flags specify an input file that contains a list of Verilog
source files. This is similar to the \fIcommand file\fP of other source files. This is similar to the \fIcommand file\fP of other
Verilog simulators, in that it is a file that contains the file names Verilog simulators, in that it is a file that contains the file names
instead of taking them on the command line. See \fBCommand Files\fP below. instead of taking them on the command line. See \fBCommand Files\fP below.

2
elab_scope.cc
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@ -793,7 +793,7 @@ void elaborate_rootscope_tasks(Design*des)
} }
cerr << cur->second->get_fileline() << ": internal error: " cerr << cur->second->get_fileline() << ": internal error: "
<< "elabortae_rootscope_tasks does not understand " << "elaborate_rootscope_tasks does not understand "
<< "this object," << endl; << "this object," << endl;
des->errors += 1; des->errors += 1;
} }

2
vhdlpp/expression_elaborate.cc
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@ -874,7 +874,7 @@ const VType* ExpName::probe_prefix_type_(Entity*ent, ScopeBase*scope) const
} }
/* /*
* This method is the probe_type() imlementation for ExpName objects * This method is the probe_type() implementation for ExpName objects
* that have prefix parts. In this case we try to get the type of the * that have prefix parts. In this case we try to get the type of the
* prefix and interpret the name in that context. * prefix and interpret the name in that context.
*/ */

2
vhdlpp/main.cc
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@ -38,7 +38,7 @@ const char COPYRIGHT[] =
* information to the file named <path>. * information to the file named <path>.
* *
* elaboration=<path> * elaboration=<path>
* Enable debugging of elaboratin by dumping elaboration * Enable debugging of elaboration by dumping elaboration
* process information to the file named <path>. * process information to the file named <path>.
* *
* entities=<path> * entities=<path>

2
vhdlpp/scope.h
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@ -169,7 +169,7 @@ class ActiveScope : public ScopeBase {
bool is_vector_name(perm_string name) const; bool is_vector_name(perm_string name) const;
// Locate the subprogram by name. The subprogram body uses // Locate the subprogram by name. The subprogram body uses
// this to locate the sobprogram declaration. Note that the // this to locate the subprogram declaration. Note that the
// subprogram may be in a package header. // subprogram may be in a package header.
SubprogramHeader* recall_subprogram(perm_string name) const; SubprogramHeader* recall_subprogram(perm_string name) const;

2
vpi/vhdl_table.c
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@ -156,7 +156,7 @@ static PLI_INT32 ivlh_attribute_event_calltf(ICARUS_VPI_CONST PLI_BYTE8*data)
rval.value.scalar = vpi1; rval.value.scalar = vpi1;
// Detect if change occured in this moment // Detect if change occurred in this moment
if (mon->last_event.high != tnow.high) if (mon->last_event.high != tnow.high)
rval.value.scalar = vpi0; rval.value.scalar = vpi0;
if (mon->last_event.low != tnow.low) if (mon->last_event.low != tnow.low)

2
vvp/dff.h
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@ -33,7 +33,7 @@
* port-2: Clock Enable input * port-2: Clock Enable input
* port-3: Asynchronous Set/Clear input. * port-3: Asynchronous Set/Clear input.
* *
* The base vvp_dff does not implement an asychronous set/clear. * The base vvp_dff does not implement an asynchronous set/clear.
*/ */
class vvp_dff : public vvp_net_fun_t { class vvp_dff : public vvp_net_fun_t {