UDPs need to evaluate their arguments before generation
When generating a .udp call the arguments need to be evaluated before the .udp is. This allows things like .resolv to be built correctly.
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@ -615,6 +615,8 @@ static void draw_udp_in_scope(ivl_net_logic_t lptr)
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static ivl_udp_t *udps = 0x0;
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static ivl_udp_t *udps = 0x0;
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static int nudps = 0;
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static int nudps = 0;
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int i;
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int i;
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unsigned ninp;
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const char **input_strings;
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for (i=0; i<nudps; i++)
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for (i=0; i<nudps; i++)
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if (udps[i] == udp)
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if (udps[i] == udp)
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@ -628,26 +630,38 @@ static void draw_udp_in_scope(ivl_net_logic_t lptr)
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draw_udp_def(udp);
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draw_udp_def(udp);
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}
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}
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fprintf(vvp_out, "L_%p .udp", lptr);
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/*
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fprintf(vvp_out, " UDP_%s",
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* We need to process the arguments first so any evaluation code
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vvp_mangle_id(ivl_udp_name(udp)));
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* (.resolv, etc.) can be built before we build the .udp call.
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draw_delay(lptr);
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* This matches what is done for the other primitives.
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*/
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for (pdx = 1 ; pdx < ivl_logic_pins(lptr) ; pdx += 1) {
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ninp = ivl_logic_pins(lptr) - 1;
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ivl_nexus_t nex = ivl_logic_pin(lptr, pdx);
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input_strings = calloc(ninp, sizeof(char*));
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for (pdx = 0 ; pdx < ninp ; pdx += 1) {
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ivl_nexus_t nex = ivl_logic_pin(lptr, pdx+1);
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/* Unlike other logic gates, primitives may have unconnected
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/* Unlike other logic gates, primitives may have unconnected
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inputs. The proper behavior is to attach a HiZ to the
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inputs. The proper behavior is to attach a HiZ to the
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port. */
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port. */
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if (nex == 0) {
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if (nex == 0) {
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assert(ivl_logic_width(lptr) == 1);
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assert(ivl_logic_width(lptr) == 1);
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fprintf(vvp_out, ", C4<z>");
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input_strings[pdx] = "C4<z>";
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} else {
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} else {
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fprintf(vvp_out, ", %s", draw_net_input(nex));
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input_strings[pdx] = draw_net_input(nex);
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}
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}
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}
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}
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fprintf(vvp_out, "L_%p .udp", lptr);
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fprintf(vvp_out, " UDP_%s",
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vvp_mangle_id(ivl_udp_name(udp)));
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draw_delay(lptr);
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for (pdx = 0 ; pdx < ninp ; pdx += 1) {
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fprintf(vvp_out, ", %s", input_strings[pdx]);
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}
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free(input_strings);
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fprintf(vvp_out, ";\n");
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fprintf(vvp_out, ";\n");
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}
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}
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@ -805,7 +819,6 @@ static void draw_logic_in_scope(ivl_net_logic_t lptr)
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input_strings[pdx] = draw_net_input(ivl_logic_pin(lptr, pdx+1));
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input_strings[pdx] = draw_net_input(ivl_logic_pin(lptr, pdx+1));
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level = 0;
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level = 0;
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ninp = ivl_logic_pins(lptr) - 1;
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while (ninp) {
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while (ninp) {
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int inst;
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int inst;
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for (inst = 0; inst < ninp; inst += 4) {
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for (inst = 0; inst < ninp; inst += 4) {
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