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Resize signed/unsigned bit vectors correctly

This commit is contained in:
Nick Gasson 2008-06-24 10:58:21 +01:00
parent 4188fbecee
commit cb08f02de1
1 changed files with 2 additions and 3 deletions
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5
tgt-vhdl/vhdl_syntax.cc
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@ -639,10 +639,9 @@ vhdl_expr *vhdl_const_bits::cast(const vhdl_type *to)
} }
else if (to->get_name() == VHDL_TYPE_SIGNED else if (to->get_name() == VHDL_TYPE_SIGNED
|| to->get_name() == VHDL_TYPE_UNSIGNED) { || to->get_name() == VHDL_TYPE_UNSIGNED) {
// Might need to drop some bits (but not extend?)
assert(to->get_width() <= get_type()->get_width());
value_.resize(to->get_width()); // Extend with sign bit
value_.resize(to->get_width(), value_[0]);
return this; return this;
} }
else if (to->get_name() == VHDL_TYPE_INTEGER) { else if (to->get_name() == VHDL_TYPE_INTEGER) {