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Update list of not implemented features.

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steve 1999-06-09 04:51:57 +00:00
parent 5047e2c3c1
commit cad3d9e4a7
1 changed files with 3 additions and 11 deletions
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README.txt
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@ -228,22 +228,16 @@ verilog features.
regval [3:1] = 3'b0; regval [3:1] = 3'b0;
regval [7:0] = 8'b0; regval [7:0] = 8'b0;
- Task Enabling isn't implemented:
Example: always @(value) // This isn't available yet.
begin
$display("value changed");
end
- The "?" operator. Example: count = val ? 1 : 0; - The "?" operator. Example: count = val ? 1 : 0;
- Ranges within parameter definitions: - Ranges within parameter definitions:
Example: parameter [15:0] seed = 16'ha3; Example: parameter [15:0] seed = 16'ha3;
[Note: IEEE Std: 1364-1995 does not allow the syntax.]
- The "&&" operator: - The "&&" operator:
Example: if (a && 0) do = 1; Example: if (a && 0) do = 1;
- Concatenation: b = { a , 4'hd };
- The "===" operator: Example: if( a === b) do = 1; - The "===" operator: Example: if( a === b) do = 1;
- The ">=" operator: Example: if ( a >= 0) do = 1; - The ">=" operator: Example: if ( a >= 0) do = 1;
@ -254,7 +248,7 @@ verilog features.
- The "<<" shift operator: Example: a = 8'b0000_0010 << 1; - The "<<" shift operator: Example: a = 8'b0000_0010 << 1;
- Min/Typ/Max assignments: Example: a = (1 : 6 : 14); - Min/Typ/Max expressions: Example: a = (1 : 6 : 14);
- Inversion of a vector with a bit operator: - Inversion of a vector with a bit operator:
Example: reg [7:0] a; a = !(8'h01); Example: reg [7:0] a; a = !(8'h01);
@ -266,8 +260,6 @@ verilog features.
- Function declarations/calls. - Function declarations/calls.
- Integer data type.
- Non-scalar memories, i.e. other than registers. - Non-scalar memories, i.e. other than registers.
Example: reg [1:0] b [2:0]; Example: reg [1:0] b [2:0];