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Statements might be emitted in wrong order

This commit is contained in:
Nick Gasson 2008-06-21 16:33:05 +01:00
parent 5cfe7ea0aa
commit c926454a41
1 changed files with 3 additions and 3 deletions
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6
tgt-vhdl/process.cc
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@ -162,6 +162,9 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
int rc = draw_stmt(vhdl_proc, vhdl_proc->get_container(), stmt); int rc = draw_stmt(vhdl_proc, vhdl_proc->get_container(), stmt);
if (rc != 0) if (rc != 0)
return rc; return rc;
// Output any remaning blocking assignments
draw_blocking_assigns(vhdl_proc);
// Initial processes are translated to VHDL processes with // Initial processes are translated to VHDL processes with
// no sensitivity list and and indefinite wait statement at // no sensitivity list and and indefinite wait statement at
@ -184,9 +187,6 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
ss << ivl_scope_tname(scope); ss << ivl_scope_tname(scope);
vhdl_proc->set_comment(ss.str()); vhdl_proc->set_comment(ss.str());
// Output any remaning blocking assignments
draw_blocking_assigns(vhdl_proc);
return 0; return 0;
} }