Add regression tests for invalid task port declarations

Check that all kinds of invalid repeated task port declarations are
detected as errors. They should not crash the application nor should they
result in successful elaboration.

The tests are created for corner cases that previously resulted in
incorrect behavior.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/task_nonansi_fail1.v

@@ -0,0 +1,15 @@
+// Check that declaring multiple task non-ANSI ports with the same name is an
+// error. Even if they both have an implicit type.
+
+module test;
+
+  task t;
+    input x;
+    input x;
+    $display("FAILED");
+  endtask
+
+  reg y;
+  initial t(y, y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail10.v

@@ -0,0 +1,17 @@
+// Check that declaring two non-ANSI task ports with an implicit type and the
+// same name is an error. Even if the signal was previously declared as an
+// variable.
+
+module test;
+
+  task t;
+    integer x;
+    input x;
+    input x;
+    $display("FAILED");
+  endtask
+
+  integer y;
+  initial t(y, y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail11.v

@@ -0,0 +1,15 @@
+// Check that declaring two non-ANSI output task ports with an explicit type is
+// an error. Even if the types are the same.
+
+module test;
+
+  task t;
+    input integer x;
+    input integer x;
+    $display("FAILED");
+  endtask
+
+  integer y;
+  initial t(y, y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail2.v

@@ -0,0 +1,16 @@
+// Check that declaring a variable multiple times for a signal that was
+// previously declared as a non-ANSI task input port is an error.
+
+module test;
+
+  task t;
+    input x;
+    reg x;
+    reg x;
+    $display("FAILED");
+  endtask
+
+  reg y;
+  initial t(y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail3.v

@@ -0,0 +1,16 @@
+// Check that declaring a variable multiple times for a signal that was
+// previously declared as a non-ANSI task output port is an error.
+
+module test;
+
+  task t;
+    output x;
+    reg x;
+    reg x;
+    $display("FAILED");
+  endtask
+
+  reg y;
+  initial t(y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail4.v

@@ -0,0 +1,16 @@
+// Check that declaring an integer typed non-ANSI task port for signal that was
+// previously declared as a variable is an error. Even if the types for both
+// declarations are the same.
+
+module test;
+
+  task t;
+    integer x;
+    input integer x;
+    $display("FAILED");
+  endtask
+
+  integer y;
+  initial t(y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail5.v

@@ -0,0 +1,15 @@
+// Check that declaring an integer typed variabe for a signal that was
+// previously declared as a non-ANSI task port is an error. Even if the types
+// for both declarations are the same.
+
+module test;
+
+  task t;
+    input integer x;
+    integer x;
+    $display("FAILED");
+  endtask
+
+  initial t();
+
+endmodule

ivtest/ivltests/task_nonansi_fail6.v

@@ -0,0 +1,16 @@
+// Check that declaring a real typed variable for a signal that was previously
+// declared as a non-ANSI task port is an error. Even if the types for both
+// declarations are the same.
+
+module test;
+
+  task t;
+    output real x;
+    real x;
+    $display("FAILED");
+  endtask
+
+  real y;
+  initial t(y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail7.v

@@ -0,0 +1,16 @@
+// Check that declaring a real typed non-ANSI task port for signal that was
+// previously declared as a variable is an error. Even if the types for both
+// declarations are the same.
+
+module test;
+
+  task t;
+    real x;
+    output real x;
+    $display("FAILED");
+  endtask
+
+  real y;
+  initial t(y);
+
+endmodule

ivtest/ivltests/task_nonansi_fail8.v

@@ -0,0 +1,14 @@
+// Check that declaring an integer typed variable for a signal that was previously
+// declared as a real typed non-ANSI task port is an error.
+
+module test;
+
+  task t;
+    output real x;
+    integer x;
+    $display("FAILED");
+  endtask
+
+  initial t();
+
+endmodule

ivtest/ivltests/task_nonansi_fail9.v

@@ -0,0 +1,15 @@
+// Check that declaring a non-ANSI task port with an explicit type for a signal
+// that was previously declared real variable is an error.
+
+module test;
+
+  task t;
+    real x;
+    output integer x;
+    $display("FAILED");
+  endtask
+
+  real y;
+  initial t(y);
+
+endmodule

ivtest/regress-vlg.list

@@ -1652,6 +1652,17 @@ task_inpad		normal			ivltests # Validates input of task should pad w/ 0
 task_iotypes		normal			ivltests # task ports with types.
 task_iotypes2		normal			ivltests # task ports with types.
 task_mem		normal			ivltests
+task_nonansi_fail1	CE			ivltests
+task_nonansi_fail2	CE			ivltests
+task_nonansi_fail3	CE			ivltests
+task_nonansi_fail4	CE			ivltests
+task_nonansi_fail5	CE			ivltests
+task_nonansi_fail6	CE			ivltests
+task_nonansi_fail7	CE			ivltests
+task_nonansi_fail8	CE			ivltests
+task_nonansi_fail9	CE			ivltests
+task_nonansi_fail10	CE			ivltests
+task_nonansi_fail11	CE			ivltests
 task_nonansi_integer1	normal			ivltests
 task_nonansi_integer2	normal			ivltests
 task_nonansi_integer_fail CE			ivltests