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Merge pull request #21 from toddstrader/master 

package imports in module headers
This commit is contained in:
Stephen Williams 2014-04-07 14:09:50 -07:00
parent 97e1151388 849ba64cf7
commit c8b20da4be
1 changed files with 21 additions and 10 deletions
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31
parse.y
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@ -1534,6 +1534,16 @@ package_declaration /* IEEE1800-2005 A.1.2 */
} }
; ;
module_package_import_list_opt
:
| package_import_list
;
package_import_list
: package_import_declaration
| package_import_list package_import_declaration
;
package_import_declaration /* IEEE1800-2005 A.2.1.3 */ package_import_declaration /* IEEE1800-2005 A.2.1.3 */
: K_import package_import_item_list ';' : K_import package_import_item_list ';'
{ } { }
@ -4104,10 +4114,11 @@ local_timeunit_prec_decl2
module module
: attribute_list_opt module_start IDENTIFIER : attribute_list_opt module_start IDENTIFIER
{ pform_startmodule(@2, $3, $2==K_program, $1); } { pform_startmodule(@2, $3, $2==K_program, $1); }
module_package_import_list_opt
module_parameter_port_list_opt module_parameter_port_list_opt
module_port_list_opt module_port_list_opt
module_attribute_foreign ';' module_attribute_foreign ';'
{ pform_module_set_ports($6); } { pform_module_set_ports($7); }
local_timeunit_prec_decl_opt local_timeunit_prec_decl_opt
{ have_timeunit_decl = true; // Every thing past here is { have_timeunit_decl = true; // Every thing past here is
have_timeprec_decl = true; // a check! have_timeprec_decl = true; // a check!
@ -4133,13 +4144,13 @@ module
} }
// Check that program/endprogram and module/endmodule // Check that program/endprogram and module/endmodule
// keywords match. // keywords match.
if ($2 != $13) { if ($2 != $14) {
switch ($2) { switch ($2) {
case K_module: case K_module:
yyerror(@13, "error: module not closed by endmodule."); yyerror(@14, "error: module not closed by endmodule.");
break; break;
case K_program: case K_program:
yyerror(@13, "error: program not closed by endprogram."); yyerror(@14, "error: program not closed by endprogram.");
break; break;
default: default:
break; break;
@ -4155,15 +4166,15 @@ module
// endlabel_opt but still have the pform_endmodule() called // endlabel_opt but still have the pform_endmodule() called
// early enough that the lexor can know we are outside the // early enough that the lexor can know we are outside the
// module. // module.
if ($15) { if ($16) {
if (strcmp($3,$15) != 0) { if (strcmp($3,$16) != 0) {
switch ($2) { switch ($2) {
case K_module: case K_module:
yyerror(@15, "error: End label doesn't match " yyerror(@16, "error: End label doesn't match "
"module name."); "module name.");
break; break;
case K_program: case K_program:
yyerror(@15, "error: End label doesn't match " yyerror(@16, "error: End label doesn't match "
"program name."); "program name.");
break; break;
default: default:
@ -4171,10 +4182,10 @@ module
} }
} }
if (($2 == K_module) && (! gn_system_verilog())) { if (($2 == K_module) && (! gn_system_verilog())) {
yyerror(@7, "error: Module end labels require " yyerror(@8, "error: Module end labels require "
"System Verilog."); "System Verilog.");
} }
delete[]$15; delete[]$16;
} }
delete[]$3; delete[]$3;
} }