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Certain expressions can convert BOOL to LOGIC 

A ternary can convert BOOL inputs to LOGIC if the select is LOGIC.
A concat is LOGIC if any of its inputs is LOGIC.
This commit is contained in:
Stephen Williams 2010-10-13 20:07:44 -07:00
parent 67000e46a8
commit c545cd3e33
3 changed files with 14 additions and 3 deletions
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12
expr_synth.cc
View File

@ -737,8 +737,16 @@ NetNet* NetEConcat::synthesize(Design*des, NetScope*scope, NetExpr*root)
tmp[idx] = parms_[idx]->synthesize(des, scope, root); tmp[idx] = parms_[idx]->synthesize(des, scope, root);
if (tmp[idx] == 0) flag = false; if (tmp[idx] == 0) flag = false;
/* Set the data type to the first one found. */ /* Set the data type to the first one found. */
if (data_type == IVL_VT_NO_TYPE) { switch (data_type) {
data_type = tmp[idx]->data_type(); case IVL_VT_NO_TYPE:
data_type = tmp[idx]->data_type();
break;
case IVL_VT_BOOL:
if (tmp[idx]->data_type()==IVL_VT_LOGIC)
data_type = IVL_VT_LOGIC;
break;
default:
break;
} }
} }
} }

4
netlist.cc
View File

@ -2359,11 +2359,13 @@ ivl_variable_type_t NetETernary::expr_type() const
ivl_assert(*this, false_val_); ivl_assert(*this, false_val_);
ivl_variable_type_t tru = true_val_->expr_type(); ivl_variable_type_t tru = true_val_->expr_type();
ivl_variable_type_t fal = false_val_->expr_type(); ivl_variable_type_t fal = false_val_->expr_type();
ivl_variable_type_t sel = cond_->expr_type();
if (tru == IVL_VT_LOGIC && fal == IVL_VT_BOOL) if (tru == IVL_VT_LOGIC && fal == IVL_VT_BOOL)
return IVL_VT_LOGIC; return IVL_VT_LOGIC;
if (tru == IVL_VT_BOOL && fal == IVL_VT_LOGIC) if (tru == IVL_VT_BOOL && fal == IVL_VT_LOGIC)
return IVL_VT_LOGIC; return IVL_VT_LOGIC;
if (sel == IVL_VT_LOGIC && (tru == IVL_VT_LOGIC || tru == IVL_VT_BOOL) && (fal == IVL_VT_LOGIC || fal == IVL_VT_BOOL))
return IVL_VT_LOGIC;
if (tru == IVL_VT_REAL && (fal == IVL_VT_LOGIC || fal == IVL_VT_BOOL)) if (tru == IVL_VT_REAL && (fal == IVL_VT_LOGIC || fal == IVL_VT_BOOL))
return IVL_VT_REAL; return IVL_VT_REAL;
if (fal == IVL_VT_REAL && (tru == IVL_VT_LOGIC || tru == IVL_VT_BOOL)) if (fal == IVL_VT_REAL && (tru == IVL_VT_LOGIC || tru == IVL_VT_BOOL))

1
vvp/logic.cc
View File

@ -24,6 +24,7 @@
# include "schedule.h" # include "schedule.h"
# include "delay.h" # include "delay.h"
# include "statistics.h" # include "statistics.h"
# include <iostream>
# include <cstring> # include <cstring>
# include <cassert> # include <cassert>
# include <cstdlib> # include <cstdlib>