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An input port driven by a variable is not collapsible

This commit is contained in:
Cary R 2020-11-30 22:44:54 -08:00
parent b7dec18088
commit c37f1c9309
4 changed files with 25 additions and 17 deletions
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2
PExpr.cc
View File

@ -72,7 +72,7 @@ NetNet* PExpr::elaborate_bi_net(Design*, NetScope*) const
return 0; return 0;
} }
bool PExpr::is_collapsible_net(Design*, NetScope*) const bool PExpr::is_collapsible_net(Design*, NetScope*, NetNet::PortType) const
{ {
return false; return false;
} }

11
PExpr.h
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@ -1,7 +1,7 @@
#ifndef IVL_PExpr_H #ifndef IVL_PExpr_H
#define IVL_PExpr_H #define IVL_PExpr_H
/* /*
* Copyright (c) 1998-2019 Stephen Williams <steve@icarus.com> * Copyright (c) 1998-2020 Stephen Williams <steve@icarus.com>
* Copyright CERN 2013 / Stephen Williams (steve@icarus.com) * Copyright CERN 2013 / Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
@ -181,7 +181,8 @@ class PExpr : public LineInfo {
// structural net that can have multiple drivers. This is // structural net that can have multiple drivers. This is
// used to test whether an input port connection can be // used to test whether an input port connection can be
// collapsed to a single wire. // collapsed to a single wire.
virtual bool is_collapsible_net(Design*des, NetScope*scope) const; virtual bool is_collapsible_net(Design*des, NetScope*scope,
NetNet::PortType port_type) const;
// This method returns true if that expression is the same as // This method returns true if that expression is the same as
// this expression. This method is used for comparing // this expression. This method is used for comparing
@ -256,7 +257,8 @@ class PEConcat : public PExpr {
NetScope*scope, NetScope*scope,
bool is_cassign, bool is_cassign,
bool is_force) const; bool is_force) const;
virtual bool is_collapsible_net(Design*des, NetScope*scope) const; virtual bool is_collapsible_net(Design*des, NetScope*scope,
NetNet::PortType port_type) const;
private: private:
NetNet* elaborate_lnet_common_(Design*des, NetScope*scope, NetNet* elaborate_lnet_common_(Design*des, NetScope*scope,
bool bidirectional_flag) const; bool bidirectional_flag) const;
@ -377,7 +379,8 @@ class PEIdent : public PExpr {
verinum* eval_const(Design*des, NetScope*sc) const; verinum* eval_const(Design*des, NetScope*sc) const;
virtual bool is_collapsible_net(Design*des, NetScope*scope) const; virtual bool is_collapsible_net(Design*des, NetScope*scope,
NetNet::PortType port_type) const;
const PPackage* package() const { return package_; } const PPackage* package() const { return package_; }

17
elab_net.cc
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1999-2014 Stephen Williams (steve@icarus.com) * Copyright (c) 1999-2020 Stephen Williams (steve@icarus.com)
* Copyright CERN 2012 / Stephen Williams (steve@icarus.com) * Copyright CERN 2012 / Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
@ -168,7 +168,8 @@ NetNet* PEConcat::elaborate_bi_net(Design*des, NetScope*scope) const
return elaborate_lnet_common_(des, scope, true); return elaborate_lnet_common_(des, scope, true);
} }
bool PEConcat::is_collapsible_net(Design*des, NetScope*scope) const bool PEConcat::is_collapsible_net(Design*des, NetScope*scope,
NetNet::PortType port_type) const
{ {
assert(scope); assert(scope);
@ -183,7 +184,7 @@ bool PEConcat::is_collapsible_net(Design*des, NetScope*scope) const
if (parms_[idx] == 0) if (parms_[idx] == 0)
return false; return false;
if (!parms_[idx]->is_collapsible_net(des, scope)) if (!parms_[idx]->is_collapsible_net(des, scope, port_type))
return false; return false;
} }
@ -1065,7 +1066,8 @@ NetNet*PEIdent::elaborate_unpacked_net(Design*des, NetScope*scope) const
return sig; return sig;
} }
bool PEIdent::is_collapsible_net(Design*des, NetScope*scope) const bool PEIdent::is_collapsible_net(Design*des, NetScope*scope,
NetNet::PortType port_type) const
{ {
assert(scope); assert(scope);
@ -1086,9 +1088,10 @@ bool PEIdent::is_collapsible_net(Design*des, NetScope*scope) const
/* If this is SystemVerilog and the variable is not yet /* If this is SystemVerilog and the variable is not yet
assigned by anything, then convert it to an unresolved assigned by anything, then convert it to an unresolved
wire. */ wire. */
if (gn_var_can_be_uwire() if (gn_var_can_be_uwire() &&
&& (sig->type() == NetNet::REG) (sig->type() == NetNet::REG) &&
&& (sig->peek_eref() == 0) ) { (sig->peek_eref() == 0) &&
(port_type == NetNet::POUTPUT)) {
sig->type(NetNet::UNRESOLVED_WIRE); sig->type(NetNet::UNRESOLVED_WIRE);
} }

12
elaborate.cc
View File

@ -1446,8 +1446,9 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
assert(prts_vector_width % instance.size() == 0); assert(prts_vector_width % instance.size() == 0);
if (!prts.empty() && (prts[0]->port_type() == NetNet::PINPUT) if (!prts.empty() && (prts[0]->port_type() == NetNet::PINPUT)
&& prts[0]->pin(0).nexus()->drivers_present() && prts[0]->pin(0).nexus()->drivers_present()
&& pins[idx]->is_collapsible_net(des, scope)) { && pins[idx]->is_collapsible_net(des, scope,
prts[0]->port_type())) {
prts[0]->port_type(NetNet::PINOUT); prts[0]->port_type(NetNet::PINOUT);
cerr << pins[idx]->get_fileline() << ": warning: input port " cerr << pins[idx]->get_fileline() << ": warning: input port "
@ -1455,9 +1456,10 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
} }
if (!prts.empty() && (prts[0]->port_type() == NetNet::POUTPUT) if (!prts.empty() && (prts[0]->port_type() == NetNet::POUTPUT)
&& (prts[0]->type() != NetNet::REG) && (prts[0]->type() != NetNet::REG)
&& prts[0]->pin(0).nexus()->has_floating_input() && prts[0]->pin(0).nexus()->has_floating_input()
&& pins[idx]->is_collapsible_net(des, scope)) { && pins[idx]->is_collapsible_net(des, scope,
prts[0]->port_type())) {
prts[0]->port_type(NetNet::PINOUT); prts[0]->port_type(NetNet::PINOUT);
cerr << pins[idx]->get_fileline() << ": warning: output port " cerr << pins[idx]->get_fileline() << ": warning: output port "