Make sig-eq-constant optimization more effective.
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steve
parent
5a2dd3393f
commit
c34e44dad0
112
elab_net.cc
112
elab_net.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elab_net.cc,v 1.162 2005/05/08 23:44:08 steve Exp $"
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#ident "$Id: elab_net.cc,v 1.163 2005/05/10 05:10:40 steve Exp $"
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#endif
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# include "config.h"
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@ -386,97 +386,52 @@ static NetNet* compare_eq_constant(Design*des, NetScope*scope,
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ones += 1;
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}
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/* Handle the special case that the gate is a compare that can
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be replaces with a reduction AND or NOR. */
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if (ones == 0 || zeros == 0) {
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NetUReduce::TYPE type;
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if (zeros > 0) {
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type = op_code == 'e'? NetUReduce::NOR : NetUReduce::OR;
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if (debug_elaborate)
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cerr << lsig->get_line() << ": debug: "
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<< "Replace net==" << val << " equality with "
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<< ones << "-input AND and "
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<< zeros << "-input NOR gates." << endl;
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<< zeros << "-input reduction [N]OR gate." << endl;
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/* Now make reduction logic to test that all the 1 bits are 1,
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and all the 0 bits are 0. The results will be ANDed
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together later, if needed. NOTE that if the compare is !=,
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and we know that we will not need an AND later, then fold
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the final invert into the reduction gate to get the right
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sense of the output. If we do need the AND later, then we
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will put the invert on that instead. */
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NetLogic*zero_gate = 0;
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NetLogic*ones_gate = 0;
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if (zeros > 0) {
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zero_gate = new NetLogic(scope,
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scope->local_symbol(), zeros + 1,
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(op_code == 'n') ? NetLogic::OR : NetLogic::NOR, 1);
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zero_gate->set_line(*lsig);
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}
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if (ones > 0) {
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ones_gate = new NetLogic(scope,
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scope->local_symbol(), ones + 1,
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(op_code == 'n') ? NetLogic::NAND : NetLogic::AND, 1);
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ones_gate->set_line(*lsig);
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} else {
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type = op_code == 'e'? NetUReduce::AND : NetUReduce::NAND;
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if (debug_elaborate)
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cerr << lsig->get_line() << ": debug: "
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<< "Replace net==" << val << " equality with "
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<< ones << "-input reduction AND gate." << endl;
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}
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unsigned zidx = 0;
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unsigned oidx = 0;
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for (unsigned idx = 0 ; idx < lsig->vector_width() ; idx += 1) {
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NetPartSelect*ps = new NetPartSelect(lsig, idx, 1,
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NetPartSelect::VP);
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ps->set_line(*lsig);
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des->add_node(ps);
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NetUReduce*red = new NetUReduce(scope, scope->local_symbol(),
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type, zeros+ones);
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des->add_node(red);
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red->set_line(*lsig);
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NetNet*tmp = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, 0, 0);
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tmp->local_flag(true);
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tmp->set_line(*lsig);
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connect(tmp->pin(0), ps->pin(0));
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if (val.get(idx) == verinum::V0) {
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zidx += 1;
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connect(zero_gate->pin(zidx), ps->pin(0));
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}
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if (val.get(idx) == verinum::V1) {
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oidx += 1;
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connect(ones_gate->pin(oidx), ps->pin(0));
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}
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connect(red->pin(1), lsig->pin(0));
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connect(red->pin(0), tmp->pin(0));
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return tmp;
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}
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NetNet*osig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, 1);
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osig->set_line(*lsig);
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osig->local_flag(true);
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if (zero_gate && ones_gate) {
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if (debug_elaborate)
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cerr << lsig->get_line() << ": debug: "
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<< "AND together AND and OR gate results" << endl;
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<< "Give up trying to replace net==" << val
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<< " equality with "
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<< ones << "-input AND and "
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<< zeros << "-input NOR gates." << endl;
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NetNet*and0_sig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, 1);
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and0_sig->set_line(*lsig);
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and0_sig->local_flag(true);
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NetNet*and1_sig = new NetNet(scope, scope->local_symbol(),
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NetNet::WIRE, 1);
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and1_sig->set_line(*lsig);
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and1_sig->local_flag(true);
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connect(and0_sig->pin(0), zero_gate->pin(0));
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connect(and1_sig->pin(0), ones_gate->pin(0));
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NetLogic*and_gate = new NetLogic(scope,
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scope->local_symbol(), 3,
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(op_code == 'n') ? NetLogic::OR : NetLogic::AND, 1);
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connect(and_gate->pin(0), osig->pin(0));
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connect(and_gate->pin(1), and0_sig->pin(0));
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connect(and_gate->pin(2), and1_sig->pin(0));
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des->add_node(and_gate);
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des->add_node(zero_gate);
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des->add_node(ones_gate);
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} else if (zero_gate) {
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connect(zero_gate->pin(0), osig->pin(0));
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des->add_node(zero_gate);
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} else {
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assert(ones_gate);
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connect(ones_gate->pin(0), osig->pin(0));
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des->add_node(ones_gate);
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}
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return osig;
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return 0;
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}
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/*
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@ -2505,6 +2460,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
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/*
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* $Log: elab_net.cc,v $
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* Revision 1.163 2005/05/10 05:10:40 steve
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* Make sig-eq-constant optimization more effective.
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*
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* Revision 1.162 2005/05/08 23:44:08 steve
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* Add support for variable part select.
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*
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