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Update README to reflect current state of Verilog/SystemVerilog support. 

Also
 - remove reference to mingw.txt, which no longer exists
 - extended types are now enabled/disabled by -gxtypes/-gno-xtypes
This commit is contained in:
Martin Whitaker 2025-08-03 15:47:53 +01:00
parent db82380cec
commit c0e44b4849
1 changed files with 15 additions and 19 deletions
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README.md
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@ -1,6 +1,6 @@
# The ICARUS Verilog Compilation System # The ICARUS Verilog Compilation System
Copyright 2000-2019 Stephen Williams Copyright 2000-2025 Stephen Williams
<details> <details>
<summary><h2>Table of Contents</h2></summary> <summary><h2>Table of Contents</h2></summary>
@ -35,10 +35,11 @@ Copyright 2000-2019 Stephen Williams
## What is ICARUS Verilog? ## What is ICARUS Verilog?
Icarus Verilog is intended to compile ALL of the Verilog HDL, as Icarus Verilog is intended to compile ALL of the Verilog HDL, as
described in the IEEE-1364 standard. Of course, it's not quite there described in the IEEE 1364 standard. Of course, it's not quite there
yet. It does currently handle a mix of structural and behavioural yet. It also compiles a (slowly growing) subset of the SystemVerilog
constructs. For a view of the current state of Icarus Verilog, see its language, as described in the IEEE 1800 standard. For a view of the
home page at https://steveicarus.github.io/iverilog/. current state of Icarus Verilog, see its home page at
https://steveicarus.github.io/iverilog/.
Icarus Verilog is not aimed at being a simulator in the traditional Icarus Verilog is not aimed at being a simulator in the traditional
sense, but a compiler that generates code employed by back-end sense, but a compiler that generates code employed by back-end
@ -55,8 +56,6 @@ system and C/C++ compilation should be able to build the source
distribution with little effort. Some actual programming skills are distribution with little effort. Some actual programming skills are
not required, but helpful in case of problems. not required, but helpful in case of problems.
> If you are building on Windows, see the mingw.txt file.
### Compile Time Prerequisites ### Compile Time Prerequisites
You can use: You can use:
@ -83,7 +82,7 @@ on a UNIX-like system:
OSX note: bison 2.3 shipped with MacOS including Catalina generates OSX note: bison 2.3 shipped with MacOS including Catalina generates
broken code, but bison 3+ works. We recommend using the Fink broken code, but bison 3+ works. We recommend using the Fink
project version of bison and flex (finkproject.org), brew version project version of bison and flex (finkproject.org), brew version
works fine either. works fine too.
- gperf 3.0 or later - gperf 3.0 or later
The lexical analyzer doesn't recognize keywords directly, The lexical analyzer doesn't recognize keywords directly,
@ -392,16 +391,12 @@ Verilog web page for the current state of support for Verilog, and in
particular, browse the bug report database for reported unsupported particular, browse the bug report database for reported unsupported
constructs. constructs.
- System functions are supported, but the return value is a little - Specify blocks are parsed but ignored by default. When enabled
tricky. See SYSTEM FUNCTION TABLE FILES in the iverilog man page. by the `-gspecify` compiler option, a subset of specify block
constructs are supported.
- Specify blocks are parsed but ignored in general.
- `trireg` is not supported. `tri0` and `tri1` are supported. - `trireg` is not supported. `tri0` and `tri1` are supported.
- tran primitives, i.e. `tran`, `tranif1`, `tranif0`, `rtran`, `rtranif1`,
and `rtranif0` are not supported.
- Net delays, of the form `wire #N foo;` do not work. Delays in - Net delays, of the form `wire #N foo;` do not work. Delays in
every other context do work properly, including the V2001 form every other context do work properly, including the V2001 form
`wire #5 foo = bar;` `wire #5 foo = bar;`
@ -409,8 +404,8 @@ constructs.
- Event controls inside non-blocking assignments are not supported. - Event controls inside non-blocking assignments are not supported.
i.e.: `a <= @(posedge clk) b;` i.e.: `a <= @(posedge clk) b;`
- Macro arguments are not supported. `` `define `` macros are supported, The list of unsupported SystemVerilog constructs is too large to
but they cannot take arguments. enumerate here.
## Nonstandard Constructs or Behaviors ## Nonstandard Constructs or Behaviors
@ -544,8 +539,9 @@ are new keywords. Typical syntax is:
reg logic bar, bat; reg logic bar, bat;
``` ```
... and so forth. The syntax can be turned off by using the ... and so forth. The syntax can be turned off by using the
`-g2` flag to iverilog, and turned on explicitly with the `-g2x` `-gxtypes` flag to iverilog, and turned on explicitly with the
flag to iverilog. `-gno-xtypes flag to iverilog. Note that this applies to standard
Verilog; SystemVerilog allows similar syntax.
## Credits ## Credits