Reorganize signal part select handling, and add support for
indexed part selects. Expand expression constant propagation to eliminate extra sums in certain cases.
This commit is contained in:
steve
parent
bebcc05aab
commit
c02b3b8ac6
29
PExpr.h
29
PExpr.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: PExpr.h,v 1.71 2005/10/04 04:09:25 steve Exp $"
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#ident "$Id: PExpr.h,v 1.72 2005/11/10 13:28:11 steve Exp $"
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#endif
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# include <string>
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@ -256,6 +256,26 @@ class PEIdent : public PExpr {
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NetScope*scope,
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const NetExpr*par,
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NetScope*found) const;
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NetExpr*elaborate_expr_net(Design*des,
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NetScope*scope,
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NetNet*net,
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NetScope*found) const;
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NetExpr*elaborate_expr_net_part_(Design*des,
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NetScope*scope,
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NetNet*net,
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NetScope*found) const;
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NetExpr*elaborate_expr_net_idx_up_(Design*des,
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NetScope*scope,
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NetNet*net,
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NetScope*found) const;
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NetExpr*elaborate_expr_net_idx_do_(Design*des,
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NetScope*scope,
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NetNet*net,
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NetScope*found) const;
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NetExpr*elaborate_expr_net_bit_(Design*des,
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NetScope*scope,
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NetNet*net,
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NetScope*found) const;
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hname_t path_;
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public:
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@ -523,6 +543,13 @@ class PECallFunction : public PExpr {
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/*
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* $Log: PExpr.h,v $
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* Revision 1.72 2005/11/10 13:28:11 steve
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* Reorganize signal part select handling, and add support for
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* indexed part selects.
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*
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* Expand expression constant propagation to eliminate extra
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* sums in certain cases.
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*
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* Revision 1.71 2005/10/04 04:09:25 steve
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* Add support for indexed select attached to parameters.
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*
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448
elab_expr.cc
448
elab_expr.cc
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 1999-2003 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: elab_expr.cc,v 1.98 2005/10/04 04:09:25 steve Exp $"
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#ident "$Id: elab_expr.cc,v 1.99 2005/11/10 13:28:11 steve Exp $"
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#endif
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# include "config.h"
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@ -504,157 +504,9 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
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// If the identifier names a signal (a register or wire)
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// then create a NetESignal node to handle it.
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if (net != 0) {
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if (net != 0)
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return elaborate_expr_net(des, scope, net, found_in);
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// If this is a part select of a signal, then make a new
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// temporary signal that is connected to just the
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// selected bits. The lsb_ and msb_ expressions are from
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// the foo[msb:lsb] expression in the original.
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if (lsb_) {
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assert(msb_);
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assert(sel_ == SEL_PART);
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verinum*lsn = lsb_->eval_const(des, scope);
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verinum*msn = msb_->eval_const(des, scope);
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if ((lsn == 0) || (msn == 0)) {
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cerr << get_line() << ": error: "
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"Part select expressions must be "
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"constant expressions." << endl;
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des->errors += 1;
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return 0;
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}
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assert(lsn);
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assert(msn);
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/* The indices of part selects are signed
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integers, so allow negative values. However,
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the width that they represent is
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unsigned. Remember that any order is possible,
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i.e., [1:0], [-4,6], etc. */
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long lsv = lsn->as_long();
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long msv = msn->as_long();
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unsigned long wid = 1 + ((msv>lsv)? (msv-lsv) : (lsv-msv));
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if (wid > net->vector_width()) {
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cerr << get_line() << ": error: part select ["
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<< msv << ":" << lsv << "] out of range."
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<< endl;
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des->errors += 1;
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delete lsn;
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delete msn;
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return 0;
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}
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assert(wid <= net->vector_width());
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if (net->sb_to_idx(msv) < net->sb_to_idx(lsv)) {
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cerr << get_line() << ": error: part select ["
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<< msv << ":" << lsv << "] out of order."
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<< endl;
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des->errors += 1;
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delete lsn;
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delete msn;
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return 0;
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}
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if (net->sb_to_idx(msv) >= net->vector_width()) {
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cerr << get_line() << ": error: part select ["
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<< msv << ":" << lsv << "] out of range."
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<< endl;
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des->errors += 1;
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delete lsn;
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delete msn;
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return 0;
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}
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NetESignal*tmp = new NetESignal(net);
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tmp->set_line(*this);
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// If the part select convers exactly the entire
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// vector, then do not bother with it. Return the
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// signal itself.
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if (net->sb_to_idx(lsv) == 0 && wid == net->vector_width())
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return tmp;
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NetExpr*ex = new NetEConst(verinum(net->sb_to_idx(lsv)));
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NetESelect*ss = new NetESelect(tmp, ex, wid);
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ss->set_line(*this);
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return ss;
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}
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// If the bit select is constant, then treat it similar
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// to the part select, so that I save the effort of
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// making a mux part in the netlist.
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verinum*msn;
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if (msb_ && (msn = msb_->eval_const(des, scope))) {
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assert(idx_ == 0);
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long msv = msn->as_long();
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unsigned idx = net->sb_to_idx(msv);
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if (idx >= net->vector_width()) {
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/* The bit select is out of range of the
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vector. This is legal, but returns a
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constant 1'bx value. */
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verinum x (verinum::Vx);
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NetEConst*tmp = new NetEConst(x);
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tmp->set_line(*this);
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cerr << get_line() << ": warning: Bit select ["
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<< msv << "] out of range of vector "
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<< net->name() << "[" << net->msb()
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<< ":" << net->lsb() << "]." << endl;
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cerr << get_line() << ": : Replacing "
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<< "expression with a constant 1'bx." << endl;
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delete msn;
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return tmp;
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}
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NetESignal*tmp = new NetESignal(net);
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tmp->set_line(*this);
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// If the vector is only one bit, we are done. The
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// bit select will return the scaler itself.
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if (net->vector_width() == 1)
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return tmp;
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// Make an expression out of the index
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NetEConst*idx_c = new NetEConst(verinum(idx));
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idx_c->set_line(*net);
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// Make a bit select with the canonical index
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NetESelect*res = new NetESelect(tmp, idx_c, 1);
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res->set_line(*net);
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return res;
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}
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NetESignal*node = new NetESignal(net);
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assert(idx_ == 0);
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// Non-constant bit select? punt and make a subsignal
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// device to mux the bit in the net. This is a fairly
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// complicated task because we need to generate
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// expressions to convert calculated bit select
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// values to canonical values that are used internally.
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if (msb_) {
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NetExpr*ex = msb_->elaborate_expr(des, scope);
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if (net->msb() < net->lsb()) {
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ex = make_sub_expr(net->lsb(), ex);
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} else {
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ex = make_add_expr(ex, - net->lsb());
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}
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NetESelect*ss = new NetESelect(node, ex, 1);
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ss->set_line(*this);
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return ss;
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}
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// All else fails, return the signal itself as the
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// expression.
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assert(msb_ == 0);
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return node;
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}
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// If the identifier names a memory, then this is a
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// memory reference and I must generate a NetEMemory
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@ -915,6 +767,291 @@ NetExpr* PEIdent::elaborate_expr_param(Design*des,
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return tmp;
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}
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/*
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* Handle part selects of NetNet identifiers.
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*/
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NetExpr* PEIdent::elaborate_expr_net_part_(Design*des, NetScope*scope,
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NetNet*net, NetScope*found_in)const
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{
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assert(lsb_ != 0);
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assert(msb_ != 0);
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assert(idx_ == 0);
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verinum*lsn = lsb_->eval_const(des, scope);
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verinum*msn = msb_->eval_const(des, scope);
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if ((lsn == 0) || (msn == 0)) {
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cerr << get_line() << ": error: "
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"Part select expressions must be "
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"constant expressions." << endl;
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des->errors += 1;
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return 0;
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}
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assert(lsn);
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assert(msn);
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/* The indices of part selects are signed integers, so allow
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negative values. However, the width that they represent is
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unsigned. Remember that any order is possible,
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i.e., [1:0], [-4:6], etc. */
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long lsv = lsn->as_long();
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long msv = msn->as_long();
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unsigned long wid = 1 + ((msv>lsv)? (msv-lsv) : (lsv-msv));
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if (wid > net->vector_width()) {
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cerr << get_line() << ": error: part select ["
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<< msv << ":" << lsv << "] out of range." << endl;
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des->errors += 1;
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delete lsn;
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delete msn;
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return 0;
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}
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assert(wid <= net->vector_width());
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if (net->sb_to_idx(msv) < net->sb_to_idx(lsv)) {
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cerr << get_line() << ": error: part select ["
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<< msv << ":" << lsv << "] out of order." << endl;
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des->errors += 1;
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delete lsn;
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delete msn;
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return 0;
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}
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if (net->sb_to_idx(msv) >= net->vector_width()) {
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cerr << get_line() << ": error: part select ["
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<< msv << ":" << lsv << "] out of range." << endl;
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des->errors += 1;
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delete lsn;
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delete msn;
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return 0;
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}
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NetESignal*tmp = new NetESignal(net);
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tmp->set_line(*this);
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// If the part select convers exactly the entire
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// vector, then do not bother with it. Return the
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// signal itself.
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if (net->sb_to_idx(lsv) == 0 && wid == net->vector_width())
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return tmp;
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NetExpr*ex = new NetEConst(verinum(net->sb_to_idx(lsv)));
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NetESelect*ss = new NetESelect(tmp, ex, wid);
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ss->set_line(*this);
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return ss;
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}
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/*
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* Part select indexed up, i.e. net[<m> +: <l>]
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*/
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NetExpr* PEIdent::elaborate_expr_net_idx_up_(Design*des, NetScope*scope,
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NetNet*net, NetScope*found_in)const
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{
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assert(lsb_ != 0);
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assert(msb_ != 0);
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assert(idx_ == 0);
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NetESignal*sig = new NetESignal(net);
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sig->set_line(*this);
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NetExpr*base = elab_and_eval(des, scope, msb_);
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NetExpr*wid_e = elab_and_eval(des, scope, lsb_);
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NetEConst*wid_c = dynamic_cast<NetEConst*> (wid_e);
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if (wid_c == 0) {
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cerr << get_line() << ": error: Width of indexed part select "
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<< "must be constant." << endl;
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cerr << get_line() << ": : Width expression is: "
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<< *wid_e << endl;
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des->errors += 1;
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return 0;
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}
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assert(wid_c != 0);
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long wid = wid_c->value().as_long();
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// Handle the special case that the base is constant as
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// well. In this case it can be converted to a conventional
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// part select.
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if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
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long lsv = base_c->value().as_long();
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// If the part select convers exactly the entire
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// vector, then do not bother with it. Return the
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// signal itself.
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if (net->sb_to_idx(lsv) == 0 && wid == net->vector_width())
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return sig;
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}
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NetESelect*ss = new NetESelect(sig, base, wid);
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ss->set_line(*this);
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if (debug_elaborate) {
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cerr << get_line() << ": debug: Elaborate part "
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<< "select base="<< *base << ", wid="<< wid << endl;
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}
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return ss;
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}
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/*
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* Part select up, i.e. net[<m> +: <l>]
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*/
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NetExpr* PEIdent::elaborate_expr_net_idx_do_(Design*des, NetScope*scope,
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NetNet*net, NetScope*found_in)const
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{
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assert(lsb_ != 0);
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assert(msb_ != 0);
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assert(idx_ == 0);
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NetESignal*sig = new NetESignal(net);
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sig->set_line(*this);
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NetExpr*base = elab_and_eval(des, scope, msb_);
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NetExpr*wid_e = elab_and_eval(des, scope, lsb_);
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NetEConst*wid_c = dynamic_cast<NetEConst*> (wid_e);
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if (wid_c == 0) {
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cerr << get_line() << ": error: Width of indexed part select "
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<< "must be constant." << endl;
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cerr << get_line() << ": : Width expression is: "
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<< *wid_e << endl;
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des->errors += 1;
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return 0;
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}
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assert(wid_c != 0);
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long wid = wid_c->value().as_long();
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// Handle the special case that the base is constant as
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// well. In this case it can be converted to a conventional
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// part select.
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if (NetEConst*base_c = dynamic_cast<NetEConst*> (base)) {
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long lsv = base_c->value().as_long();
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// If the part select convers exactly the entire
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// vector, then do not bother with it. Return the
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// signal itself.
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if (net->sb_to_idx(lsv) == (wid-1) && wid == net->vector_width())
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return sig;
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}
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NetExpr*base_adjusted = wid > 1? make_add_expr(base,1-wid) : base;
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NetESelect*ss = new NetESelect(sig, base_adjusted, wid);
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ss->set_line(*this);
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if (debug_elaborate) {
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cerr << get_line() << ": debug: Elaborate part "
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<< "select base="<< *base << ", wid="<< wid << endl;
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}
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return ss;
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}
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NetExpr* PEIdent::elaborate_expr_net_bit_(Design*des, NetScope*scope,
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NetNet*net, NetScope*found_in) const
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{
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assert(msb_ != 0);
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assert(lsb_ == 0);
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assert(idx_ == 0);
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// If the bit select is constant, then treat it similar
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// to the part select, so that I save the effort of
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// making a mux part in the netlist.
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if (verinum*msn = msb_->eval_const(des, scope)) {
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long msv = msn->as_long();
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unsigned idx = net->sb_to_idx(msv);
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if (idx >= net->vector_width()) {
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/* The bit select is out of range of the
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vector. This is legal, but returns a
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constant 1'bx value. */
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verinum x (verinum::Vx);
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NetEConst*tmp = new NetEConst(x);
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tmp->set_line(*this);
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cerr << get_line() << ": warning: Bit select ["
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<< msv << "] out of range of vector "
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<< net->name() << "[" << net->msb()
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<< ":" << net->lsb() << "]." << endl;
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cerr << get_line() << ": : Replacing "
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<< "expression with a constant 1'bx." << endl;
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delete msn;
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return tmp;
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}
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NetESignal*tmp = new NetESignal(net);
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tmp->set_line(*this);
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// If the vector is only one bit, we are done. The
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// bit select will return the scaler itself.
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if (net->vector_width() == 1)
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return tmp;
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// Make an expression out of the index
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NetEConst*idx_c = new NetEConst(verinum(idx));
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idx_c->set_line(*net);
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// Make a bit select with the canonical index
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NetESelect*res = new NetESelect(tmp, idx_c, 1);
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res->set_line(*net);
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return res;
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}
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NetESignal*node = new NetESignal(net);
|
||||
|
||||
// Non-constant bit select? punt and make a subsignal
|
||||
// device to mux the bit in the net. This is a fairly
|
||||
// complicated task because we need to generate
|
||||
// expressions to convert calculated bit select
|
||||
// values to canonical values that are used internally.
|
||||
NetExpr*ex = msb_->elaborate_expr(des, scope);
|
||||
|
||||
if (net->msb() < net->lsb()) {
|
||||
ex = make_sub_expr(net->lsb(), ex);
|
||||
} else {
|
||||
ex = make_add_expr(ex, - net->lsb());
|
||||
}
|
||||
|
||||
NetESelect*ss = new NetESelect(node, ex, 1);
|
||||
ss->set_line(*this);
|
||||
return ss;
|
||||
}
|
||||
|
||||
NetExpr* PEIdent::elaborate_expr_net(Design*des, NetScope*scope,
|
||||
NetNet*net, NetScope*found_in) const
|
||||
{
|
||||
// If this is a part select of a signal, then make a new
|
||||
// temporary signal that is connected to just the
|
||||
// selected bits. The lsb_ and msb_ expressions are from
|
||||
// the foo[msb:lsb] expression in the original.
|
||||
if (sel_ == SEL_PART)
|
||||
return elaborate_expr_net_part_(des, scope, net, found_in);
|
||||
|
||||
if (sel_ == SEL_BIT)
|
||||
return elaborate_expr_net_bit_(des, scope, net, found_in);
|
||||
|
||||
if (sel_ == SEL_IDX_UP)
|
||||
return elaborate_expr_net_idx_up_(des, scope, net, found_in);
|
||||
|
||||
if (sel_ == SEL_IDX_DO)
|
||||
return elaborate_expr_net_idx_do_(des, scope, net, found_in);
|
||||
|
||||
// It's not anything else, so this must be a simple identifier
|
||||
// expression with no part or bit select. Return the signal
|
||||
// itself as the expression.
|
||||
assert(sel_ == SEL_NONE);
|
||||
assert(msb_ == 0);
|
||||
assert(lsb_ == 0);
|
||||
assert(idx_ == 0);
|
||||
|
||||
NetESignal*node = new NetESignal(net);
|
||||
node->set_line(*this);
|
||||
return node;
|
||||
}
|
||||
|
||||
NetEConst* PENumber::elaborate_expr(Design*des, NetScope*, bool) const
|
||||
{
|
||||
assert(value_);
|
||||
|
|
@ -1091,6 +1228,13 @@ NetExpr* PEUnary::elaborate_expr(Design*des, NetScope*scope, bool) const
|
|||
|
||||
/*
|
||||
* $Log: elab_expr.cc,v $
|
||||
* Revision 1.99 2005/11/10 13:28:11 steve
|
||||
* Reorganize signal part select handling, and add support for
|
||||
* indexed part selects.
|
||||
*
|
||||
* Expand expression constant propagation to eliminate extra
|
||||
* sums in certain cases.
|
||||
*
|
||||
* Revision 1.98 2005/10/04 04:09:25 steve
|
||||
* Add support for indexed select attached to parameters.
|
||||
*
|
||||
|
|
|
|||
11
elaborate.cc
11
elaborate.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: elaborate.cc,v 1.330 2005/09/27 04:51:37 steve Exp $"
|
||||
#ident "$Id: elaborate.cc,v 1.331 2005/11/10 13:28:11 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -587,7 +587,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
|
|||
|
||||
if (debug_elaborate) {
|
||||
cerr << get_line() << ": debug: Instantiate module "
|
||||
<< rmod->mod_name() << " With instance name "
|
||||
<< rmod->mod_name() << " with instance name "
|
||||
<< get_name() << " in scope " << scope->name() << endl;
|
||||
}
|
||||
|
||||
|
|
@ -3028,6 +3028,13 @@ Design* elaborate(list<perm_string>roots)
|
|||
|
||||
/*
|
||||
* $Log: elaborate.cc,v $
|
||||
* Revision 1.331 2005/11/10 13:28:11 steve
|
||||
* Reorganize signal part select handling, and add support for
|
||||
* indexed part selects.
|
||||
*
|
||||
* Expand expression constant propagation to eliminate extra
|
||||
* sums in certain cases.
|
||||
*
|
||||
* Revision 1.330 2005/09/27 04:51:37 steve
|
||||
* Error message for invalid for-loop index variable.
|
||||
*
|
||||
|
|
|
|||
51
eval_tree.cc
51
eval_tree.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: eval_tree.cc,v 1.65 2005/09/14 02:53:14 steve Exp $"
|
||||
#ident "$Id: eval_tree.cc,v 1.66 2005/11/10 13:28:12 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -55,10 +55,11 @@ NetEConst* NetEBAdd::eval_tree()
|
|||
{
|
||||
eval_sub_tree_();
|
||||
NetEConst*lc = dynamic_cast<NetEConst*>(left_);
|
||||
if (lc == 0) return 0;
|
||||
NetEConst*rc = dynamic_cast<NetEConst*>(right_);
|
||||
if (rc == 0) return 0;
|
||||
|
||||
/* If both operands are constant, then replace the entire
|
||||
expression with a constant value. */
|
||||
if (lc != 0 && rc != 0) {
|
||||
verinum lval = lc->value();
|
||||
verinum rval = rc->value();
|
||||
|
||||
|
|
@ -77,6 +78,43 @@ NetEConst* NetEBAdd::eval_tree()
|
|||
return new NetEConst(val);
|
||||
}
|
||||
|
||||
/* Try to combine a right constant value with the right
|
||||
constant value of a sub-expression add. For example, the
|
||||
expression (a + 2) - 1 can be rewritten as a + 1. */
|
||||
|
||||
NetEBAdd*se = dynamic_cast<NetEBAdd*>(left_);
|
||||
lc = se? dynamic_cast<NetEConst*>(se->right_) : 0;
|
||||
|
||||
if (lc != 0 && rc != 0) {
|
||||
assert(se != 0);
|
||||
verinum lval = lc->value();
|
||||
verinum rval = rc->value();
|
||||
|
||||
verinum val;
|
||||
if (op_ == se->op_) {
|
||||
/* (a + lval) + rval --> a + (rval+lval) */
|
||||
/* (a - lval) - rval --> a - (rval+lval) */
|
||||
val = rval + lval;
|
||||
} else {
|
||||
/* (a - lval) + rval --> a + (rval-lval) */
|
||||
/* (a + lval) - rval --> a - (rval-lval) */
|
||||
val = rval - lval;
|
||||
}
|
||||
|
||||
NetEConst*tmp = new NetEConst(val);
|
||||
left_ = se->left_->dup_expr();
|
||||
delete se;
|
||||
delete right_;
|
||||
right_ = tmp;
|
||||
/* We've changed the subexpression, but the result is
|
||||
still not constant, so return nil here anyhow. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Nothing more to be done, the value is not constant. */
|
||||
return 0;
|
||||
}
|
||||
|
||||
NetEConst* NetEBBits::eval_tree()
|
||||
{
|
||||
eval_sub_tree_();
|
||||
|
|
@ -1561,6 +1599,13 @@ NetEConst* NetEUReduce::eval_tree()
|
|||
|
||||
/*
|
||||
* $Log: eval_tree.cc,v $
|
||||
* Revision 1.66 2005/11/10 13:28:12 steve
|
||||
* Reorganize signal part select handling, and add support for
|
||||
* indexed part selects.
|
||||
*
|
||||
* Expand expression constant propagation to eliminate extra
|
||||
* sums in certain cases.
|
||||
*
|
||||
* Revision 1.65 2005/09/14 02:53:14 steve
|
||||
* Support bool expressions and compares handle them optimally.
|
||||
*
|
||||
|
|
|
|||
7
parse.y
7
parse.y
|
|
@ -1,7 +1,7 @@
|
|||
|
||||
%{
|
||||
/*
|
||||
* Copyright (c) 1998-2004 Stephen Williams (steve@icarus.com)
|
||||
* Copyright (c) 1998-2005 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: parse.y,v 1.206 2005/10/04 04:09:25 steve Exp $"
|
||||
#ident "$Id: parse.y,v 1.207 2005/11/10 13:28:12 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -985,6 +985,7 @@ expr_primary
|
|||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
tmp->msb_ = $3;
|
||||
tmp->sel_ = PEIdent::SEL_BIT;
|
||||
delete $1;
|
||||
$$ = tmp;
|
||||
}
|
||||
|
|
@ -1455,6 +1456,7 @@ lavalue
|
|||
} else {
|
||||
tmp->msb_ = sel;
|
||||
}
|
||||
tmp->sel_ = PEIdent::SEL_BIT;
|
||||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
delete $1;
|
||||
|
|
@ -1465,6 +1467,7 @@ lavalue
|
|||
assert($2->count() == 2);
|
||||
tmp->msb_ = (*$2)[0];
|
||||
tmp->lsb_ = (*$2)[1];
|
||||
tmp->sel_ = PEIdent::SEL_PART;
|
||||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
delete $1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue