Add -g2012 flag and keywords for IEEE 1800-2012.
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@ -141,6 +141,7 @@ enum generation_t {
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GN_VER2005 = 4,
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GN_VER2005_SV = 5,
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GN_VER2009 = 6,
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GN_VER2012 = 7,
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GN_DEFAULT = 4
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};
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@ -178,7 +179,8 @@ extern bool gn_strict_expr_width_flag;
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static inline bool gn_var_can_be_uwire(void)
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{
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if (generation_flag == GN_VER2005_SV ||
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generation_flag == GN_VER2009)
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generation_flag == GN_VER2009 ||
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generation_flag == GN_VER2012)
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return true;
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return false;
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}
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@ -186,7 +188,8 @@ static inline bool gn_var_can_be_uwire(void)
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static inline bool gn_system_verilog(void)
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{
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if (generation_flag == GN_VER2005_SV ||
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generation_flag == GN_VER2009)
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generation_flag == GN_VER2009 ||
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generation_flag == GN_VER2012)
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return true;
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return false;
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}
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@ -207,6 +210,7 @@ enum { GN_KEYWORDS_1364_1995 = 0x0001,
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GN_KEYWORDS_VAMS_2_3 = 0x0010,
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GN_KEYWORDS_1800_2005 = 0x0020,
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GN_KEYWORDS_1800_2009 = 0x0040,
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GN_KEYWORDS_1800_2012 = 0x0080,
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GN_KEYWORDS_ICARUS = 0x8000
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};
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extern int lexor_keyword_mask;
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@ -1,4 +1,4 @@
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.TH iverilog 1 "February 27th, 2011" "" "Version %M.%m.%n %E"
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.TH iverilog 1 "April 2nd, 2013" "" "Version %M.%m.%n %E"
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.SH NAME
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iverilog - Icarus Verilog compiler
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@ -6,7 +6,7 @@ iverilog - Icarus Verilog compiler
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.B iverilog
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[\-ESVv] [\-Bpath] [\-ccmdfile|\-fcmdfile] [\-Dmacro[=defn]]
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[\-Pparameter=value] [\-pflag=value]
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[\-dname] [\-g1995|\-g2001|\-g2005|\-g2005-sv|\-g2009|\-g<feature>]
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[\-dname] [\-g1995|\-g2001|\-g2005|\-g2005-sv|\-g2009|\-g2012|\-g<feature>]
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[\-Iincludedir] [\-mmodule] [\-M[mode=]file] [\-Nfile] [\-ooutputfilename]
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[\-stopmodule] [\-ttype] [\-Tmin/typ/max] [\-Wclass] [\-ypath] sourcefile
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@ -61,10 +61,11 @@ is the Verilog input, but with file inclusions and macro references
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expanded and removed. This is useful, for example, to preprocess
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Verilog source for use by other compilers.
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.TP 8
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.B -g1995\fI|\fP-g2001\fI|\fP-g2001-noconfig\fI|\fP-g2005\fI|\fP-g2005-sv\fI|\fP-g2009
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.B -g1995\fI|\fP-g2001\fI|\fP-g2001-noconfig\fI|\fP-g2005\fI|\fP-g2005-sv\fI|\fP-g2009\fI|\fP-g2012
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Select the Verilog language \fIgeneration\fP to support in the compiler.
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This selects between \fIIEEE1364\-1995\fP, \fIIEEE1364\-2001\fP,
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\fIIEEE1364\-2005\fP, \fIIEEE1800\-2005\fP, or \fIIEEE1800\-2009\fP.
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\fIIEEE1364\-2005\fP, \fIIEEE1800\-2005\fP, \fIIEEE1800\-2009\fP, or
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\fIIEEE1800\-2012\fP.
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Icarus Verilog currently defaults to the \fIIEEE1364\-2005\fP generation
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of the language. This flag is used to restrict the language to a set of
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keywords/features, this allows simulation of older Verilog code that may
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2000-2011 Stephen Williams (steve@icarus.com)
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* Copyright (c) 2000-2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -39,7 +39,7 @@ const char NOTICE[] =
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const char HELP[] =
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"Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]\n"
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" [-g1995|-g2001|-g2005|-g2005-sv|-g2009] [-g<feature>]\n"
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" [-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012] [-g<feature>]\n"
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" [-D macro[=defn]] [-I includedir]\n"
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" [-M [mode=]depfile] [-m module]\n"
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" [-N file] [-o filename] [-p flag=value]\n"
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@ -642,6 +642,9 @@ int process_generation(const char*name)
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else if (strcmp(name,"2009") == 0)
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generation = "2009";
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else if (strcmp(name,"2012") == 0)
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generation = "2012";
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else if (strcmp(name,"1") == 0) { /* Deprecated: use 1995 */
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generation = "1995";
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gen_xtypes = "no-xtypes";
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@ -720,6 +723,7 @@ int process_generation(const char*name)
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" 2005 -- IEEE1364-2005\n"
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" 2005-sv -- IEEE1800-2005\n"
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" 2009 -- IEEE1800-2009\n"
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" 2012 -- IEEE1800-2012\n"
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"Other generation flags:\n"
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" specify | no-specify\n"
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" verilog-ams | no-verilog-ams\n"
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@ -1031,7 +1035,7 @@ int main(int argc, char **argv)
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if (version_flag || verbose_flag) {
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printf("Icarus Verilog version " VERSION " (" VERSION_TAG ")\n\n");
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printf("Copyright 1998-2011 Stephen Williams\n\n");
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printf("Copyright 1998-2013 Stephen Williams\n\n");
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puts(NOTICE);
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}
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@ -1057,10 +1061,11 @@ int main(int argc, char **argv)
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fprintf(iconfig_file, "sys_func:%s%csystem.sft\n", base, sep);
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fprintf(iconfig_file, "sys_func:%s%cvhdl_sys.sft\n", base, sep);
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/* If verilog-2005/9 is enabled or icarus-misc or verilog-ams,
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/* If verilog-2005/09/12 is enabled or icarus-misc or verilog-ams,
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* then include the v2005_math library. */
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if (strcmp(generation, "2005") == 0 ||
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strcmp(generation, "2009") == 0 ||
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strcmp(generation, "2012") == 0 ||
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strcmp(gen_icarus, "icarus-misc") == 0 ||
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strcmp(gen_verilog_ams, "verilog-ams") == 0) {
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fprintf(iconfig_file, "sys_func:%s%cv2005_math.sft\n", base, sep);
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@ -1076,7 +1081,8 @@ int main(int argc, char **argv)
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/* If verilog-2009 (SystemVerilog) is enabled, then include the
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v2009 module. */
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if (strcmp(generation, "2005-sv") == 0 ||
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strcmp(generation, "2009") == 0) {
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strcmp(generation, "2009") == 0 ||
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strcmp(generation, "2012") == 0) {
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fprintf(iconfig_file, "sys_func:%s%cv2009.sft\n", base, sep);
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fprintf(iconfig_file, "module:v2009\n");
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}
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12
lexor.lex
12
lexor.lex
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@ -4,7 +4,7 @@
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%{
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/*
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* Copyright (c) 1998-2012 Stephen Williams (steve@icarus.com)
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* Copyright (c) 1998-2013 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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@ -399,7 +399,7 @@ TU [munpf]
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/* This rule handles scaled time values for SystemVerilog. */
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[0-9][0-9_]*(\.[0-9][0-9_]*)?{TU}?s {
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if(generation_flag & (GN_VER2005_SV | GN_VER2009)) {
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if(generation_flag & (GN_VER2005_SV | GN_VER2009 | GN_VER2012)) {
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yylval.text = strdupnew(yytext);
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return TIME_LITERAL;
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} else REJECT; }
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@ -572,6 +572,14 @@ TU [munpf]
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|GN_KEYWORDS_1364_2005
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|GN_KEYWORDS_1800_2005
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|GN_KEYWORDS_1800_2009;
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} else if (strcmp(word,"1800-2012") == 0) {
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lexor_keyword_mask = GN_KEYWORDS_1364_1995
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|GN_KEYWORDS_1364_2001
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|GN_KEYWORDS_1364_2001_CONFIG
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|GN_KEYWORDS_1364_2005
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|GN_KEYWORDS_1800_2005
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|GN_KEYWORDS_1800_2009
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|GN_KEYWORDS_1800_2012;
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} else if (strcmp(word,"VAMS-2.3") == 0) {
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lexor_keyword_mask = GN_KEYWORDS_1364_1995
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|GN_KEYWORDS_1364_2001
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@ -161,6 +161,7 @@ ifnone, GN_KEYWORDS_1364_1995, K_ifnone
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ignore_bins, GN_KEYWORDS_1800_2005, K_ignore_bins
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illegal_bins, GN_KEYWORDS_1800_2005, K_illegal_bins
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implies, GN_KEYWORDS_1800_2009, K_implies
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implements, GN_KEYWORDS_1800_2012, K_implements
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import, GN_KEYWORDS_1800_2005, K_import
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incdir, GN_KEYWORDS_1364_2001_CONFIG, K_incdir
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include, GN_KEYWORDS_1364_2001_CONFIG, K_include
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@ -173,6 +174,7 @@ inside, GN_KEYWORDS_1800_2005, K_inside
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instance, GN_KEYWORDS_1364_2001_CONFIG, K_instance
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int, GN_KEYWORDS_1800_2005, K_int
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integer, GN_KEYWORDS_1364_1995, K_integer
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interconnect, GN_KEYWORDS_1800_2012, K_interconnect
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interface, GN_KEYWORDS_1800_2005, K_interface
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intersect, GN_KEYWORDS_1800_2005, K_intersect
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join, GN_KEYWORDS_1364_1995, K_join
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@ -207,6 +209,7 @@ nand, GN_KEYWORDS_1364_1995, K_nand
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nature, GN_KEYWORDS_VAMS_2_3, K_nature
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negedge, GN_KEYWORDS_1364_1995, K_negedge
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net_resolution, GN_KEYWORDS_VAMS_2_3, K_net_resolution
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nettype, GN_KEYWORDS_1800_2012, K_nettype
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new, GN_KEYWORDS_1800_2005, K_new
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nexttime, GN_KEYWORDS_1800_2009, K_nexttime
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nmos, GN_KEYWORDS_1364_1995, K_nmos
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@ -274,6 +277,7 @@ sin, GN_KEYWORDS_VAMS_2_3, K_sin
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sinh, GN_KEYWORDS_VAMS_2_3, K_sinh
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slew, GN_KEYWORDS_VAMS_2_3, K_slew
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small, GN_KEYWORDS_1364_1995, K_small
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soft, GN_KEYWORDS_1800_2012, K_soft
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solve, GN_KEYWORDS_1800_2005, K_solve
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specify, GN_KEYWORDS_1364_1995, K_specify
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specparam, GN_KEYWORDS_1364_1995, K_specparam
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8
main.cc
8
main.cc
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@ -286,6 +286,9 @@ static void process_generation_flag(const char*gen)
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} else if (strcmp(gen,"2009") == 0) {
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generation_flag = GN_VER2009;
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} else if (strcmp(gen,"2012") == 0) {
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generation_flag = GN_VER2012;
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} else if (strcmp(gen,"icarus-misc") == 0) {
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gn_icarus_misc_flag = true;
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@ -901,6 +904,8 @@ int main(int argc, char*argv[])
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lexor_keyword_mask = 0;
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switch (generation_flag) {
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case GN_VER2012:
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lexor_keyword_mask |= GN_KEYWORDS_1800_2012;
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case GN_VER2009:
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lexor_keyword_mask |= GN_KEYWORDS_1800_2009;
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case GN_VER2005_SV:
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@ -945,6 +950,9 @@ int main(int argc, char*argv[])
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case GN_VER2009:
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cout << "IEEE1800-2009";
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break;
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case GN_VER2012:
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cout << "IEEE1800-2012";
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break;
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}
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if (gn_verilog_ams_flag)
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3
parse.y
3
parse.y
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@ -490,6 +490,9 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%token K_s_nexttime K_s_until K_s_until_with K_strong K_sync_accept_on
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%token K_sync_reject_on K_unique0 K_until K_until_with K_untyped K_weak
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/* The new tokens from 1800-2012. */
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%token K_implements K_interconnect K_nettype K_soft
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/* The new tokens for Verilog-AMS 2.3. */
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%token K_above K_abs K_absdelay K_abstol K_access K_acos K_acosh
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/* 1800-2005 has defined "assert" above! */
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2
pform.cc
2
pform.cc
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@ -922,7 +922,7 @@ void pform_startmodule(const struct vlltype&loc, const char*name,
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void pform_check_timeunit_prec()
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{
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assert(! pform_cur_module.empty());
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if ((generation_flag & (GN_VER2005_SV | GN_VER2009)) &&
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if ((generation_flag & (GN_VER2005_SV | GN_VER2009 | GN_VER2012)) &&
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(pform_cur_module.front()->time_unit < pform_cur_module.front()->time_precision)) {
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VLerror("error: a timeprecision is missing or is too large!");
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} else assert(pform_cur_module.front()->time_unit >=
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