luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix Cygwin compile problem (replace abs() call with ?: 

This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
This commit is contained in:
Cary R 2011-11-11 16:22:56 -08:00 committed by Stephen Williams
parent 4fe7561e74
commit bcb963a235
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
vhdlpp/expression_emit.cc
View File

@ -94,7 +94,8 @@ int ExpAggregate::emit_array_(ostream&out, Entity*ent, Architecture*arc, const V
rc_lsb = rang.lsb()->evaluate(ent, arc, use_lsb); rc_lsb = rang.lsb()->evaluate(ent, arc, use_lsb);
if (rc_msb && rc_lsb) { if (rc_msb && rc_lsb) {
int asize = abs(use_msb - use_lsb) + 1; int asize = (use_msb >= use_lsb) ? (use_msb - use_lsb) + 1 :
(use_lsb - use_msb) + 1;
out << "{" << asize << "{"; out << "{" << asize << "{";
errors += aggregate_[0].expr->emit(out, ent, arc); errors += aggregate_[0].expr->emit(out, ent, arc);
out << "}}"; out << "}}";