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iverilog
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Skip the , in module lists.

This commit is contained in:
steve 2001-05-14 00:55:31 +00:00
parent bf96986c38
commit bc6dfeb4a9
1 changed files with 2 additions and 1 deletions
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3
tgt-vvp/vvp.c
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: vvp.c,v 1.5 2001/04/28 20:06:07 steve Exp $" #ident "$Id: vvp.c,v 1.6 2001/05/14 00:55:31 steve Exp $"
#endif #endif
/* /*
@ -52,6 +52,7 @@ inline static void draw_module_declarations(ivl_design_t des)
fprintf(vvp_out, ":vpi_module \"%s\";\n", buffer); fprintf(vvp_out, ":vpi_module \"%s\";\n", buffer);
cp = comma; cp = comma;
if (*cp) cp += 1;
} }
} }