Add regression tests for parameter declarations shadowing type identifiers

Check that visible type identifiers can be shadowed by value parameter names
and by type parameter names. Cover ordinary parameter declarations, typed
parameter declarations, and parameter port list declarations separately.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/sv_type_identifier_parameter_decl_name.v

@@ -0,0 +1,35 @@
+// Check that parameter declaration names can shadow visible type identifiers.
+
+typedef int L;
+typedef int P;
+typedef int Q;
+typedef int R;
+
+module test;
+
+  reg failed;
+
+  parameter P = 7, R = 13;
+  localparam Q = 11, L = 17;
+
+  `define check(value, expected, error) \
+    if ((value) !== (expected)) begin \
+      $display("FAILED(%0d). %s", `__LINE__, error); \
+      $display("  expected %0h, got %0h", expected, value); \
+      failed = 1'b1; \
+    end
+
+  initial begin
+    failed = 1'b0;
+
+    `check(P, 7, "parameter name did not hide typedef");
+    `check(R, 13, "parameter list continuation did not hide typedef");
+    `check(Q, 11, "localparam name did not hide typedef");
+    `check(L, 17, "localparam list continuation did not hide typedef");
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/ivltests/sv_type_identifier_parameter_port_name.v

@@ -0,0 +1,85 @@
+// Check that parameter port declaration names can shadow visible type identifiers.
+
+typedef int P;
+typedef int Q;
+typedef int R;
+typedef logic [7:0] T;
+typedef int TP;
+
+package p;
+  typedef logic [5:0] PT;
+endpackage
+
+`define check(value, expected, error) \
+  if ((value) !== (expected)) begin \
+    $display("FAILED(%0d). %s", `__LINE__, error); \
+    $display("  expected %0h, got %0h", expected, value); \
+    failed = 1'b1; \
+  end
+
+module M #(
+  parameter int P = 5,
+  Q = 9,
+  int R = 13,
+  T typed_value = 8'ha5,
+  T T = 8'h3c,
+  p::PT pkg_value = 6'h2a,
+  parameter type TP = logic [5:0]
+) (output reg failed);
+
+  TP type_param_value;
+
+  initial begin
+    failed = 1'b0;
+    type_param_value = 6'h15;
+
+    `check(P, 5, "parameter port typed value mismatch");
+    `check(Q, 9, "parameter port untyped continuation mismatch");
+    `check(R, 13, "parameter port atomic type continuation mismatch");
+    `check($bits(typed_value), 8, "parameter port typedef type continuation width mismatch");
+    `check(typed_value, 8'ha5, "parameter port typedef type continuation value mismatch");
+    `check($bits(T), 8, "parameter port type-name continuation did not keep typedef type");
+    `check(T, 8'h3c, "parameter port type-name continuation value mismatch");
+    `check($bits(pkg_value), 6, "parameter port package type continuation width mismatch");
+    `check(pkg_value, 6'h2a, "parameter port package type continuation value mismatch");
+    `check($bits(type_param_value), 6, "parameter port type parameter mismatch");
+    `check(type_param_value, 6'h15, "parameter port type parameter value mismatch");
+  end
+
+endmodule
+
+module N #(P = 3, T typed_value = 8'h5a) (output reg failed);
+
+  initial begin
+    failed = 1'b0;
+
+    `check(P, 3, "omitted parameter keyword mismatch");
+    `check($bits(typed_value), 8, "omitted parameter keyword typedef width mismatch");
+    `check(typed_value, 8'h5a, "omitted parameter keyword typedef value mismatch");
+  end
+
+endmodule
+
+module test;
+
+  reg failed;
+  wire failed_m;
+  wire failed_n;
+
+  M i_m(failed_m);
+  N i_n(failed_n);
+
+  initial begin
+    failed = 1'b0;
+
+    #1;
+
+    `check(failed_m, 1'b0, "parameter port module failed");
+    `check(failed_n, 1'b0, "omitted parameter keyword module failed");
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/ivltests/sv_type_identifier_parameter_type_decl_name.v

@@ -0,0 +1,41 @@
+// Check that typed parameter declaration names can shadow visible type identifiers.
+
+typedef int P;
+typedef logic [7:0] T;
+typedef logic [6:0] U;
+
+module test;
+
+  reg failed;
+
+  parameter int P = 13;
+  parameter T typed_value = 8'ha5;
+  parameter T T = 8'h3c;
+  parameter U u0 = 7'h2a, U = 7'h15;
+
+  `define check(value, expected, error) \
+    if ((value) !== (expected)) begin \
+      $display("FAILED(%0d). %s", `__LINE__, error); \
+      $display("  expected %0h, got %0h", expected, value); \
+      failed = 1'b1; \
+    end
+
+  initial begin
+    failed = 1'b0;
+
+    `check(P, 13, "typed parameter name did not hide typedef");
+    `check($bits(typed_value), 8, "typed parameter width mismatch");
+    `check(typed_value, 8'ha5, "typed parameter value mismatch");
+    `check($bits(T), 8, "type-name parameter did not keep typedef type");
+    `check(T, 8'h3c, "type-name parameter value mismatch");
+    `check($bits(u0), 7, "parameter list first declaration did not keep typedef type");
+    `check(u0, 7'h2a, "parameter list first value mismatch");
+    `check($bits(U), 7, "parameter list continuation did not allow typedef name as parameter name");
+    `check(U, 7'h15, "parameter list continuation value mismatch");
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/ivltests/sv_type_identifier_parameter_type_param_name.v

@@ -0,0 +1,32 @@
+// Check that type parameter declaration names can shadow visible type identifiers.
+
+typedef int TP;
+
+module test;
+
+  reg failed;
+
+  parameter type TP = logic [3:0];
+
+  TP type_param_value;
+
+  `define check(value, expected, error) \
+    if ((value) !== (expected)) begin \
+      $display("FAILED(%0d). %s", `__LINE__, error); \
+      $display("  expected %0h, got %0h", expected, value); \
+      failed = 1'b1; \
+    end
+
+  initial begin
+    failed = 1'b0;
+    type_param_value = 4'hc;
+
+    `check($bits(type_param_value), 4, "type parameter name did not hide typedef");
+    `check(type_param_value, 4'hc, "type parameter value mismatch");
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/regress-vvp.list

@@ -389,6 +389,10 @@ sv_type_identifier_modport_name	vvp_tests/sv_type_identifier_modport_name.json
 sv_type_identifier_module_name	vvp_tests/sv_type_identifier_module_name.json
 sv_type_identifier_net_name	vvp_tests/sv_type_identifier_net_name.json
 sv_type_identifier_package_item	vvp_tests/sv_type_identifier_package_item.json
+sv_type_identifier_parameter_decl_name	vvp_tests/sv_type_identifier_parameter_decl_name.json
+sv_type_identifier_parameter_port_name	vvp_tests/sv_type_identifier_parameter_port_name.json
+sv_type_identifier_parameter_type_decl_name	vvp_tests/sv_type_identifier_parameter_type_decl_name.json
+sv_type_identifier_parameter_type_param_name	vvp_tests/sv_type_identifier_parameter_type_param_name.json
 sv_type_identifier_port_name	vvp_tests/sv_type_identifier_port_name.json
 sv_type_identifier_specparam_name	vvp_tests/sv_type_identifier_specparam_name.json
 sv_type_identifier_task_function_argument_name	vvp_tests/sv_type_identifier_task_function_argument_name.json

ivtest/vvp_tests/sv_type_identifier_parameter_decl_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_parameter_decl_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_parameter_port_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_parameter_port_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_parameter_type_decl_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_parameter_type_decl_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_parameter_type_param_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_parameter_type_param_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}