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When padding logic constants, sign extend x/z properly. 

If there is an x or z bin in the sign position of a logic number to
be padded, pad with the x or z, not zero.
This commit is contained in:
Stephen Williams 2008-05-09 08:25:25 -07:00
parent 73dcace781
commit bbed408d68
2 changed files with 2 additions and 3 deletions
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3
net_expr.cc
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@ -81,6 +81,7 @@ NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r, bool lossless_flag)
}
unsigned pad_width = lossless_flag? 1 : 0;
cast_signed(l->has_sign() && r->has_sign());
/* Now that we have the operand sizes the way we like, or as
good as we are going to get them, set the size of myself. */
@ -91,8 +92,6 @@ NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r, bool lossless_flag)
} else {
expr_width(l->expr_width() + pad_width);
}
cast_signed(l->has_sign() && r->has_sign());
}
NetEBAdd::~NetEBAdd()

2
verinum.cc
View File

@ -448,7 +448,7 @@ verinum pad_to_width(const verinum&that, unsigned width)
verinum::V pad = that[that.len()-1];
if (pad==verinum::V1 && !that.has_sign())
pad = verinum::V0;
if (that.has_len()) {
if (that.has_len() && !that.has_sign()) {
if (pad==verinum::Vx)
pad = verinum::V0;
if (pad==verinum::Vz)