Add an extensions.txt file.

README.txt

@@ -359,7 +359,8 @@ constructs.
 Icarus Verilog includes some features that are not part of the
 IEEE1364 standard, but have well defined meaning, and also sometimes
 gives nonstandard (but extended) meanings to some features of the
-language that are defined.
+language that are defined. See the "extensions.txt" documentation for
+more details.
 
     $is_signed(<expr>)
 	This system function returns 1 if the expression contained is
@@ -493,52 +494,3 @@ Verilog guidance, and especially testing from many people. Testers in
 particular include a larger community of people interested in a GPL
 Verilog for Linux.
 
-
-6.1 PORT MAINTAINERS
-
-This is a list of people who have created ports and precompiled
-packages for various operating systems. These folks have graciously
-taken on the task of building Icarus Verilog on their systems and
-bundled it into neat packages.(+) If you want to be added to the list (or
-removed from the list) send e-mail to me.
-
-      FreeBSD/{Intel,alpha}
-	Ying-Chieh Liao <ijliao@FreeBSD.org>
-
-      Linux/{alpha,AMD64,Intel} (RPMS)
-	Stephen Williams <steve@icarus.com>
-
-      Linux/* (.debs)
-	Hamish Moffatt <hamish@rising.com.au>
-
-      Macintosh -- MacO/S
-	Yasuhisa Kato <kato@y.email.ne.jp>
-
-      Mac O/S X
-        Timothy J. Wood <tjw@omnigroup.com>
-
-      NetBSD/*
-	Dan McMahill <mcmahill@mtl.mit.edu>
-
-      Solaris/SPARC packages (.pkg)
-	Dan McMahill <mcmahill@mtl.mit.edu>
-
-      Cygwin32/*
-        Venkat Iyer <venkat@comit.com>
-
-      Mingw32
-        Venkat Iyer <venkat@comit.com>
-
-(+) These are not the only systems where Icarus Verilog has been run,
-just the systems where precompiled binaries are publicly available.
-
-
-6.2 TEST SUITE MANAGER
-
-Steve Wilson <stevew@ka6s.com> has taken on the large task of managing
-the test suite. He has maintained the regression test scripts, the
-driver list, received submissions from myself and others, and has
-written a great many tests on his own. Any compiler writer, for any
-language, will tell you that the test suite is at least as important
-as the compiler code itself.
-

extensions.txt

@@ -0,0 +1,84 @@
+
+Icarus Verilog Extensions
+
+Icarus Verilog supports certain extensions to the baseline IEEE1364
+standard. Some of these are picked from extended variants of the
+language, such as SystemVerilog, and some are expressions of internal
+behavior of Icarus Verilog, made available as a tool debugging aid.
+
+* Builtin System Functions
+
+** Extended Verilog Data Types
+
+This feature is turned off if the generation flag "-g" is set to other
+then the default "2x".  For example, "iverilog -g2x" enables extended
+data types, and "iverilog -g2" disables them.
+
+Icarus Verilog adds support for extended data types. This extended
+type syntax is based on a proposal by Cadence Design Systems,
+originally as an update to the IEEE1364. That original proposal has
+apparently been absorbed by the IEEE1800 SystemVerilog
+standard. Icarus Verilog currently only takes the new primitive types
+from the proposal.
+
+Extended data types seperates the concept of net/variable from the
+data type. Both nets and variables can declared with any data
+type. The primitive types avaialable are:
+
+    logic  - The familiar 0, 1, x and z, optionally with strength.
+    bool   - Limited to only 0 and 1
+    real   - 64bit real values
+
+Nets with logic type may have multiple drivers with strength, and the
+value is resolved the usual way. Only logic values may be driven to
+logic nets, so bool values driven onto logic nets are implicitly
+converted to logic.
+
+Nets with any other type may not have multiple drivers. The compiler
+should detect the multiple drivers and report an error.
+
+- Declarations
+
+The declaration of a net is extended to include the type of the wire,
+with the syntax:
+
+    wire <type> <wire-assignment-list>... ;
+
+The <type>, if omitted, is taken to be logic. The "wire" can be any of
+the net keywords. Wires can be logic, bool, real, or vectors of logic
+or bool. Some valid examples:
+
+    wire real foo = 1.0;
+    tri logic bus[31:0];
+    wire bool addr[23:0];
+    ... and so on.
+
+The declarations of variables is similar. The "reg" keyword is used to
+specify that this is a variable. Variables can have the same data
+types as nets.
+
+- Ports
+
+Module and task ports in standard verilog are restricted to logic
+types. This extension removes that restriction, allowing any type to
+pass through the port consistent with the continuous assignment
+connectivity that is implied by the type.
+
+- Expressions
+
+Expressions in the face of real values is covered by the baseline
+Verilog standard.
+
+The bool type supports the same operators as the logic type, with the
+obvious differences imposed by th limited domain.
+
+Comparison operators (not case compare) return logic if either of
+their operands is logic. If both are bool or real (including mix of
+bool and real) then the result is bool. This is because comparison of
+bools and reals always return exactly true or false.
+
+Case comparison returns bool. This differs from baseline Verilog,
+which strictly speaking returns a logic, but only 0 or 1 values.
+
+All the arithmetic operators return bool if both of their operands are
+bool. Otherwise, they return logic.