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Stub code for handling logic gates

This commit is contained in:
Nick Gasson 2008-06-09 14:08:27 +01:00
parent 7120ab7b13
commit b96e471fa2
2 changed files with 13 additions and 1 deletions
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12
tgt-vhdl/scope.cc
View File

@ -25,6 +25,15 @@
#include <sstream> #include <sstream>
#include <cassert> #include <cassert>
/*
* Translate all the primitive logic gates into concurrent
* signal assignments.
*/
static void declare_logic(vhdl_arch *arch, ivl_scope_t scope)
{
}
/* /*
* Declare all signals for a scope in an architecture. * Declare all signals for a scope in an architecture.
*/ */
@ -71,6 +80,9 @@ static vhdl_entity *create_entity_for(ivl_scope_t scope)
// the architecture // the architecture
declare_signals(arch, scope); declare_signals(arch, scope);
// Similarly, add all the primitive logic gates
declare_logic(arch, scope);
// Build a comment to add to the entity/architecture // Build a comment to add to the entity/architecture
std::ostringstream ss; std::ostringstream ss;
ss << "Generated from Verilog module " << ivl_scope_tname(scope); ss << "Generated from Verilog module " << ivl_scope_tname(scope);

2
tgt-vhdl/vhdl_syntax.cc
View File

@ -315,7 +315,7 @@ void vhdl_signal_decl::emit(std::ofstream &of, int level) const
vhdl_expr::~vhdl_expr() vhdl_expr::~vhdl_expr()
{ {
if (type != NULL) if (type_ != NULL)
delete type_; delete type_;
} }