Add the verilog.sh script.
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@ -6,6 +6,7 @@ ivl
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dep
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dep
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configure
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configure
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Makefile
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Makefile
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verilog
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config.status
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config.status
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config.log
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config.log
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config.cache
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config.cache
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18
Makefile.in
18
Makefile.in
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@ -18,7 +18,7 @@
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# 59 Temple Place - Suite 330
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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# Boston, MA 02111-1307, USA
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#
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#
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#ident "$Id: Makefile.in,v 1.13 1999/08/15 02:20:06 steve Exp $"
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#ident "$Id: Makefile.in,v 1.14 1999/08/17 15:57:43 steve Exp $"
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#
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#
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#
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#
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SHELL = /bin/sh
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SHELL = /bin/sh
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@ -45,7 +45,7 @@ CPPFLAGS = @CPPFLAGS@ @DEFS@
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CXXFLAGS = @CXXFLAGS@
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CXXFLAGS = @CXXFLAGS@
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LDFLAGS = @LDFLAGS@
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LDFLAGS = @LDFLAGS@
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all: ivl
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all: ivl verilog
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cd vpi ; make all
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cd vpi ; make all
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cd vvm ; make all
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cd vvm ; make all
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cd ivlpp ; make all
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cd ivlpp ; make all
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@ -68,6 +68,14 @@ $(FF) $(TT)
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Makefile: Makefile.in config.status
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Makefile: Makefile.in config.status
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./config.status
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./config.status
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# Make the actual verilog program from the script template. This
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# simply invloves editing the substitution strings in the script into
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# the configured copy.
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tmp1 = bindir
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tmp2 = libdir
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verilog: $(srcdir)/verilog.sh
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sed -e 's;@$(tmp1)@;@bindir@;' -e 's;@$(tmp2)@;@libdir@;' < $< > $@
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ivl: $O
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ivl: $O
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$(CXX) $(CXXFLAGS) -o ivl $O
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$(CXX) $(CXXFLAGS) -o ivl $O
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@ -88,11 +96,14 @@ parse.h parse.cc: parse.y
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lexor.cc: lexor.lex
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lexor.cc: lexor.lex
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flex -PVL -s -olexor.cc lexor.lex
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flex -PVL -s -olexor.cc lexor.lex
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install: all installdirs $(bindir)/ivl
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install: all installdirs $(bindir)/verilog $(bindir)/ivl
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cd vpi ; make install
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cd vpi ; make install
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cd vvm ; make install
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cd vvm ; make install
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cd ivlpp ; make install
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cd ivlpp ; make install
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$(bindir)/verilog: ./verilog
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$(INSTALL_PROGRAM) ./verilog $(bindir)/verilog
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$(bindir)/ivl: ivl
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$(bindir)/ivl: ivl
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$(INSTALL_PROGRAM) ./ivl $(bindir)/ivl
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$(INSTALL_PROGRAM) ./ivl $(bindir)/ivl
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@ -101,6 +112,7 @@ installdirs: mkinstalldirs
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uninstall:
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uninstall:
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rm -f $(bindir)/ivl
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rm -f $(bindir)/ivl
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rm -f $(bindir)/verilog
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cd vpi ; make uninstall
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cd vpi ; make uninstall
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cd vvm ; make uninstall
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cd vvm ; make uninstall
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cd ivlpp ; make uninstall
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cd ivlpp ; make uninstall
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@ -0,0 +1,98 @@
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#!/bin/sh
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# verilog - A wrapper shell script for ivl
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# Copyright (C) 1999 Stefan Petersen (spe@geda.seul.org)
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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# Setup variables
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execPath=@bindir@
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execIVLPP=${execPath}/ivlpp
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execIVL=${execPath}/ivl
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execCpp=/usr/bin/g++
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target="-t vvm"
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tmpDir=/tmp
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tmpPPFile=${tmpDir}/ivl$$.pp
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tmpCCFile=${tmpDir}/ivl$$.cc
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VPIModulePath=@libdir@/ivl:.
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outputRequested=0
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# If VPI module path aren't set up, setup default
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# Humm, doesn't work as intended ... silly silly me
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if test -z "${VPI_MODULE_PATH}" ; then
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VPI_MODULE_PATH=${VPIModulePath} ;
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export VPI_MODULE_PATH ;
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fi
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# Try to extract given parameters
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for parameter in $*; do
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# echo ${parameter} ;
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if test ${outputRequested} -eq 1 ; then
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outputFile=${parameter};
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outputRequested=0;
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else
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case "${parameter}" in
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-D*) extDefines="${extDefines} ${parameter}" ;;
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-I*) extIncPath="${extIncPath} -I ${parameter:2}";;
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-l*) extLibPath="${extLibPath} ${parameter}" ;;
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-o) outputRequested=1 ;;
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*) verilogFile=${parameter};;
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esac
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fi
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done
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# If no output file is given should we guess one or...?
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if test -z "${outputFile}" ; then
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outputFile=`echo ${verilogFile} | sed -e 's/\(.*\)\..*/\1/'`;
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fi
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# Preprocess
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${execIVLPP} ${extDefines} ${extIncPath} -L -o ${tmpPPFile} ${verilogFile}
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if test $? -ne 0 ; then
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echo "Preprocessing failed. Terminating compilation."
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rm -f ${tmpPPFile}
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exit -1
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fi
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# Compile preprocessed verilog file
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${execIVL} ${target} -o ${tmpCCFile} ${tmpPPFile}
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if test $? -ne 0 ; then
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echo "Verilog compilation failed. Terminating compilation."
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rm -f ${tmpCCFile}
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exit -1
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fi
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rm -f ${tmpPPFile}
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# Compile generated C++ code
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${execCpp} -rdynamic ${tmpCCFile} -o ${outputFile} -lvvm -ldl
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if test $? -ne 0 ; then
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echo "C++ compilation failed. Terminating compilation."
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rm -f ${tmpCCFile}
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exit -1
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fi
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rm -f ${tmpCCFile}
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