luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix segfault in wildcard port connection with unnamed port (issue #530). 

A module port list may contain unnamed entries, e.g.

  module dut(a,);

When performing a wildcard connection, these entries should be skipped,
as there is no name to match.

(cherry picked from commit 061121203b)
This commit is contained in:
Martin Whitaker 2021-07-30 17:42:16 +01:00
parent d3b0992a22
commit b48cdff89e
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
elaborate.cc
View File

@ -1200,7 +1200,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
// Handle wildcard named port // Handle wildcard named port
if (pins_[idx].name[0] == '*') { if (pins_[idx].name[0] == '*') {
for (unsigned j = 0 ; j < nexp ; j += 1) { for (unsigned j = 0 ; j < nexp ; j += 1) {
if ((!pins[j]) && (!pins_is_explicitly_not_connected[j])) { if (rmod->ports[j] && !pins[j] && !pins_is_explicitly_not_connected[j]) {
pins_fromwc[j] = true; pins_fromwc[j] = true;
NetNet* net = 0; NetNet* net = 0;
const NetExpr*par = 0; const NetExpr*par = 0;