Merge pull request #11 from muhammadjawadkhan/feat/randomize-unconstrained
SV: unconstrained randomize() / rand vertical slice
This commit is contained in:
commit
b27828d5a6
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@ -9,7 +9,7 @@ Each item should be a dedicated `feat/<name>` branch, with tests/examples and a
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3. **Virtual interfaces** + eventing on `vif.clk` — **partial** (see [virtual-interface.md](virtual-interface.md))
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4. **Clocking blocks** — enough for `@(vif.cb)` — **partial** (interface-local `@(bif.cb)`; see [clocking.md](clocking.md))
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5. **`mailbox` / `semaphore` builtins** (or solid class equivalents with blocking put/get) — **partial** (int mailbox + semaphore; see [mailbox-semaphore.md](mailbox-semaphore.md))
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6. **Constraints + `randomize()` / `randomize() with`** — start unconstrained `rand`, then solver
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6. **Constraints + `randomize()` / `randomize() with`** — **partial** (unconstrained `rand`/`randc` only; see [randomize.md](randomize.md)); solver / `with` still missing
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7. **`$cast` / `$typename` hardening** for factory patterns
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8. **Covergroups** — functional coverage
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9. **DPI-C** — optional but common in real flows
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@ -18,7 +18,7 @@ Last updated: 2026-07-21
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| Virtual interfaces | **Partial** on `feat/virtual-interface`: `virtual interface T` as class property / TF arg; assign interface instance; member R/W; `@(posedge vif.clk)`. See [`docs/virtual-interface.md`](virtual-interface.md) and [`examples/virtual_interface`](../examples/virtual_interface). |
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| Clocking blocks | **Partial** on `feat/clocking-blocks`: interface-local `clocking`; `@(bif.cb)`; `cb.sig` R/W with `#0` skew. See [`docs/clocking.md`](clocking.md) and [`examples/clocking`](../examples/clocking). |
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| Mailbox / semaphore | **Partial** on `feat/mailbox-semaphore`: compiler builtins; `mailbox #(int)` + blocking/nonblocking put/get/num; `semaphore` get/put/try_get. See [`docs/mailbox-semaphore.md`](mailbox-semaphore.md) and [`examples/mailbox_sem`](../examples/mailbox_sem). |
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| Constraints / randomize | Missing |
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| Constraints / randomize | **Partial** on `feat/randomize-unconstrained`: unconstrained `rand`/`randc` integral props via `obj.randomize()` (returns 1). No constraint solver / `with` yet. See [`docs/randomize.md`](randomize.md) and [`examples/randomize`](../examples/randomize). |
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| Covergroups / DPI | Missing |
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## Remotes
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@ -0,0 +1,52 @@
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# Unconstrained `randomize()` / `rand` (Tier A #6, first slice)
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Status: **partial** — unconstrained integral `rand`/`randc` only; no constraint solver.
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## Supported in this slice
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```systemverilog
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class pkt;
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rand bit [7:0] a;
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rand bit [3:0] b;
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bit [7:0] c; // non-rand left alone
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function new(); c = 8'h11; endfunction
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endclass
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pkt p = new;
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bit ok = p.randomize(); // returns 1; assigns random values to a,b
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```
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- `obj.randomize()` returns `1` on success (null / unknown class type → `0`)
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- Assigns random 0/1 bits to all `rand` and `randc` **integral** (`bit`/`logic`/`reg` packed) instance properties
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- Non-rand properties are unchanged
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- `randc` is treated like `rand` for now (no cyclic guarantee)
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## Encoding
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| Layer | Role |
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|-------|------|
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| Parse | `rand`/`randc` already property qualifiers; `constraint` / `randomize() with` remain **sorry** |
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| Elab | `obj.randomize()` → `$ivl_randomize(obj)` (expr or task) |
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| Target API | `ivl_type_prop_rand()` exposes qualifiers to codegen |
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| Codegen | `%urandom <wid>` + `%store/prop/v` per rand property |
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| Runtime | `%urandom` fills vec4 with RNG bits (`std::mt19937`) |
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## Deferred (do not claim)
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- Constraint blocks / solver
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- `randomize() with { ... }`
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- `rand_mode` / `constraint_mode`
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- True `randc` cyclic behavior
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- Randomizing non-integral properties (reals, strings, class handles, arrays)
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- `std::randomize` procedural form / inline constraints
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## Example
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[`examples/randomize/randomize_basic.sv`](../examples/randomize/randomize_basic.sv) — prints `PASSED`.
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```bash
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./install/bin/iverilog -g2012 -o /tmp/rand.vvp examples/randomize/randomize_basic.sv
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./install/bin/vvp /tmp/rand.vvp
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```
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See also [STATUS.md](STATUS.md) and [ROADMAP.md](ROADMAP.md).
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23
elab_expr.cc
23
elab_expr.cc
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@ -2036,6 +2036,14 @@ unsigned PECallFunction::test_width_method_(Design*, NetScope*,
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signed_flag_ = false;
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return expr_width_;
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}
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/* Built-in unconstrained randomize() -> bit success. */
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if (method_name == "randomize") {
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expr_type_ = IVL_VT_BOOL;
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expr_width_ = 1;
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min_width_ = 1;
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signed_flag_ = false;
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return expr_width_;
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}
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NetScope*method = class_type->method_from_name(method_name);
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if (method == 0) {
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@ -4198,6 +4206,21 @@ NetExpr* PECallFunction::elaborate_expr_method_(Design*des, NetScope*scope,
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return sys;
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}
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/* Unconstrained std::randomize vertical slice: assign random
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values to rand/randc integral properties; return 1. */
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if (method_name == perm_string::literal("randomize")) {
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if (!parms_.empty()) {
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cerr << get_fileline() << ": sorry: randomize() with "
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<< "arguments is not supported yet." << endl;
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des->errors += 1;
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}
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NetESFunc*sys = new NetESFunc("$ivl_randomize",
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&netvector_t::scalar_logic, 1);
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sys->set_line(*this);
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sys->parm(0, sub_expr);
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return sys;
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}
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return elaborate_class_method_net_(des, scope, net, class_type,
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method_name, nullptr);
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}
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10
elaborate.cc
10
elaborate.cc
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@ -4642,6 +4642,16 @@ NetProc* PCallTask::elaborate_method_(Design*des, NetScope*scope,
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: sem_one_parm);
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}
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}
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if (method_name == perm_string::literal("randomize")) {
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static const std::vector<perm_string> no_parms;
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if (!parms_.empty()) {
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cerr << get_fileline() << ": sorry: randomize() with "
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<< "arguments is not supported yet." << endl;
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des->errors += 1;
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}
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return elaborate_sys_task_method_(des, scope, net, method_name,
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"$ivl_randomize", no_parms);
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}
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NetScope*task = class_type->method_from_name(method_name);
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if (task == 0) {
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// If an implicit this was added it is not an error if we
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@ -0,0 +1,22 @@
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# Build/run unconstrained randomize smoke test against this tree's install.
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ROOT ?= $(abspath ../..)
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PREFIX ?= $(ROOT)/install
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IVERILOG ?= $(PREFIX)/bin/iverilog
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VVP ?= $(PREFIX)/bin/vvp
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VVP_MOD ?= $(PREFIX)/lib/ivl
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OUT := randomize_basic.vvp
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.PHONY: all run clean
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all: $(OUT)
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$(OUT): randomize_basic.sv
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$(IVERILOG) -g2012 -o $@ $<
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run: $(OUT)
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$(VVP) -M $(VVP_MOD) $(OUT)
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clean:
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rm -f $(OUT)
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@ -0,0 +1,25 @@
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// Unconstrained class.randomize() / rand vertical slice smoke test.
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class pkt;
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rand bit [7:0] a;
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rand bit [3:0] b;
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bit [7:0] c;
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function new();
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c = 8'h11;
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endfunction
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endclass
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module top;
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pkt p;
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bit ok;
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initial begin
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p = new;
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ok = p.randomize();
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if (!ok) $fatal(1, "randomize failed");
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// a,b should be randomized (not X); c unchanged
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if (p.a === 8'hxx) $fatal(1, "rand a still X");
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if (p.b === 4'hx) $fatal(1, "rand b still X");
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if (p.c !== 8'h11) $fatal(1, "non-rand mutated");
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$display("a=%0h b=%0h c=%0h", p.a, p.b, p.c);
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$display("PASSED");
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end
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endmodule
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@ -2401,6 +2401,8 @@ extern const char* ivl_type_name(ivl_type_t net);
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extern int ivl_type_properties(ivl_type_t net);
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extern const char* ivl_type_prop_name(ivl_type_t net, int idx);
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extern ivl_type_t ivl_type_prop_type(ivl_type_t net, int idx);
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/* Return 1 if property is rand, 2 if randc, 0 otherwise. */
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extern int ivl_type_prop_rand(ivl_type_t net, int idx);
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/* Maximum element count for a queue type (0 = unbounded). Only valid
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* when ivl_type_base(net) == IVL_VT_QUEUE. */
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13
t-dll-api.cc
13
t-dll-api.cc
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@ -3315,6 +3315,19 @@ extern "C" ivl_type_t ivl_type_prop_type(ivl_type_t net, int idx)
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return class_type->get_prop_type(idx);
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}
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extern "C" int ivl_type_prop_rand(ivl_type_t net, int idx)
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{
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const netclass_t*class_type = dynamic_cast<const netclass_t*>(net);
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assert(class_type);
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property_qualifier_t qual = class_type->get_prop_qual(idx);
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if (qual.test_randc())
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return 2;
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if (qual.test_rand())
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return 1;
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return 0;
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}
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extern "C" unsigned ivl_type_queue_max(ivl_type_t net)
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{
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if (net == 0) return 0;
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@ -38,6 +38,62 @@ void resize_vec4_wid(ivl_expr_t expr, unsigned wid)
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fprintf(vvp_out, " %%pad/u %u;\n", wid);
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}
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/*
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* Unconstrained randomize: for each rand/randc integral property of
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* the class, push random bits and store into the property. Leaves a
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* 1-bit success (1) on the vec4 stack when leave_result is set.
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*/
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void draw_ivl_randomize(ivl_expr_t obj, int leave_result)
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{
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ivl_type_t cls = ivl_expr_net_type(obj);
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int idx;
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if (cls == 0 && ivl_expr_type(obj) == IVL_EX_SIGNAL) {
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ivl_signal_t sig = ivl_expr_signal(obj);
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if (sig)
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cls = ivl_signal_net_type(sig);
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}
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draw_eval_object(obj);
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if (cls == 0 || ivl_type_base(cls) != IVL_VT_CLASS) {
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fprintf(vvp_out, " %%pop/obj 1, 0;\n");
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if (leave_result)
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fprintf(vvp_out, " %%pushi/vec4 0, 0, 1;\n");
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return;
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}
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for (idx = 0 ; idx < ivl_type_properties(cls) ; idx += 1) {
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ivl_type_t ptype;
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ivl_variable_type_t pbase;
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unsigned wid;
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if (ivl_type_prop_rand(cls, idx) == 0)
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continue;
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ptype = ivl_type_prop_type(cls, idx);
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if (ptype == 0)
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continue;
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pbase = ivl_type_base(ptype);
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if (pbase != IVL_VT_BOOL && pbase != IVL_VT_LOGIC)
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continue;
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wid = ivl_type_packed_width(ptype);
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if (wid == 0)
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wid = 1;
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fprintf(vvp_out, " %%urandom %u; randomize prop %s\n",
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wid, ivl_type_prop_name(cls, idx));
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if (pbase == IVL_VT_BOOL)
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fprintf(vvp_out, " %%cast2;\n");
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fprintf(vvp_out, " %%store/prop/v %d, %u;\n", idx, wid);
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}
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fprintf(vvp_out, " %%pop/obj 1, 0;\n");
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if (leave_result)
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fprintf(vvp_out, " %%pushi/vec4 1, 0, 1;\n");
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}
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/*
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* Test if the draw_immediate_vec4 instruction can be used.
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*/
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@ -1270,6 +1326,18 @@ static void draw_sfunc_vec4(ivl_expr_t expr)
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return;
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}
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/* Unconstrained class.randomize(): fill rand/randc integral props. */
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if (strcmp(ivl_expr_name(expr), "$ivl_randomize") == 0) {
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ivl_expr_t obj = (parm_count > 0) ? ivl_expr_parm(expr, 0) : 0;
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if (obj)
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draw_ivl_randomize(obj, 1);
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else
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fprintf(vvp_out, " %%pushi/vec4 0, 0, 1;\n");
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if (ivl_expr_width(expr) > 1)
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fprintf(vvp_out, " %%pad/u %u;\n", ivl_expr_width(expr));
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return;
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}
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draw_vpi_func_call(expr);
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}
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@ -208,6 +208,11 @@ extern uint64_t get_number_immediate64(ivl_expr_t ex);
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* evaluation is the vec4 result in the top of the vec4 expression stack.
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*/
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extern void draw_eval_vec4(ivl_expr_t ex);
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/* Emit unconstrained class randomize for $ivl_randomize(obj).
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* Leaves a 1-bit success flag on the vec4 stack when leave_result!=0;
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* otherwise pops the result (task form). */
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extern void draw_ivl_randomize(ivl_expr_t obj, int leave_result);
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extern void resize_vec4_wid(ivl_expr_t expr, unsigned wid);
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/*
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@ -2048,6 +2048,13 @@ static int show_system_task_call(ivl_statement_t net)
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return 0;
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}
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if (strcmp(stmt_name, "$ivl_randomize") == 0) {
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ivl_expr_t obj = ivl_stmt_parm(net, 0);
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if (obj)
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draw_ivl_randomize(obj, 0);
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return 0;
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}
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if (strcmp(stmt_name, "$ivl_semaphore$get") == 0) {
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ivl_expr_t sem = ivl_stmt_parm(net, 0);
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if (sem) draw_eval_object(sem);
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@ -186,6 +186,7 @@ extern bool of_SEM_PUT(vthread_t thr, vvp_code_t code);
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extern bool of_SEM_TRY_GET(vthread_t thr, vvp_code_t code);
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extern bool of_BOX_VEC4(vthread_t thr, vvp_code_t code);
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extern bool of_UNBOX_VEC4(vthread_t thr, vvp_code_t code);
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extern bool of_URANDOM(vthread_t thr, vvp_code_t code);
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extern bool of_NOOP(vthread_t thr, vvp_code_t code);
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extern bool of_NOR(vthread_t thr, vvp_code_t code);
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extern bool of_NORR(vthread_t thr, vvp_code_t code);
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@ -403,6 +403,7 @@ static const struct opcode_table_s opcode_table[] = {
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{ "%test_nul/obj", of_TEST_NUL_OBJ, 0,{OA_NONE, OA_NONE, OA_NONE} },
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{ "%test_nul/prop",of_TEST_NUL_PROP,2,{OA_NUMBER, OA_BIT1, OA_NONE} },
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{ "%unbox/vec4",of_UNBOX_VEC4,1, {OA_NUMBER, OA_NONE, OA_NONE} },
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{ "%urandom", of_URANDOM, 1, {OA_NUMBER, OA_NONE, OA_NONE} },
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{ "%vif/load/vec4", of_VIF_LOAD_VEC4, 2,{OA_NUMBER, OA_BIT1, OA_NONE} },
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{ "%vif/store/vec4",of_VIF_STORE_VEC4,2,{OA_NUMBER, OA_BIT1, OA_NONE} },
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{ "%vif/wait", of_VIF_WAIT, 2,{OA_NUMBER, OA_BIT1, OA_NONE} },
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@ -37,6 +37,7 @@
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# include <set>
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# include <typeinfo>
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# include <vector>
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# include <random>
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# include <cstdlib>
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# include <climits>
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# include <cstring>
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@ -8632,3 +8633,30 @@ bool of_UNBOX_VEC4(vthread_t thr, vvp_code_t cp)
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thr->push_vec4(res);
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return true;
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}
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/*
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* %urandom <wid>
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*
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* Push <wid> bits of unconstrained random 0/1 onto the vec4 stack.
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* Used by unconstrained class.randomize().
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*/
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bool of_URANDOM(vthread_t thr, vvp_code_t cp)
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{
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static std::mt19937 rng(std::random_device{}());
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unsigned wid = cp->number;
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vvp_vector4_t val(wid);
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unsigned bit = 0;
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while (bit < wid) {
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uint32_t r = rng();
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unsigned chunk = (wid - bit) < 32 ? (wid - bit) : 32;
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for (unsigned i = 0 ; i < chunk ; i += 1) {
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val.set_bit(bit + i, (r & 1u) ? BIT4_1 : BIT4_0);
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r >>= 1;
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}
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bit += chunk;
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}
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thr->push_vec4(val);
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return true;
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}
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