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Support negedge flip-flops in synthesis and in vvp.

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Also extend the support for FF asynchronous set values to vvp and
fix the dff functor in vvp to correctly model asynchronous set/clr
behaviour.
This commit is contained in:
Martin Whitaker
2015-06-13 16:47:57 +01:00
parent d39c284055
commit b242663cae
19 changed files with 356 additions and 214 deletions
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t-dll.cc
+11 -2
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@@ -1938,6 +1938,9 @@ void dll_target::lpm_ff(const NetFF*net)
const Nexus*nex;
/* Set the clock polarity. */
obj->u_.ff.negedge_flag = net->is_negedge();
/* Set the clk signal to point to the nexus, and the nexus to
point back to this device. */
nex = net->pin_Clock().nexus();
@@ -1976,7 +1979,10 @@ void dll_target::lpm_ff(const NetFF*net)
nexus_lpm_add(obj->u_.ff.aset, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
verinum tmp = net->aset_value();
obj->u_.ff.aset_value = expr_from_value_(tmp);
if (tmp.len() > 0)
obj->u_.ff.aset_value = expr_from_value_(tmp);
else
obj->u_.ff.aset_value = 0;
} else {
obj->u_.ff.aset = 0;
@@ -2001,7 +2007,10 @@ void dll_target::lpm_ff(const NetFF*net)
nexus_lpm_add(obj->u_.ff.sset, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
verinum tmp = net->sset_value();
obj->u_.ff.sset_value = expr_from_value_(tmp);
if (tmp.len() > 0)
obj->u_.ff.sset_value = expr_from_value_(tmp);
else
obj->u_.ff.sset_value = 0;
} else {
obj->u_.ff.sset = 0;