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Handle procedural conditional, and some 

of the conditional expressions.

 Elaborate signals and identifiers differently,
 allowing the netlist to hold signal information.
This commit is contained in:
steve 1998-11-07 17:05:05 +00:00
parent 5836c8aa4b
commit b118634189
18 changed files with 496 additions and 41 deletions
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10
PExpr.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: PExpr.h,v 1.1 1998/11/03 23:28:54 steve Exp $"
#ident "$Id: PExpr.h,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include <string>
@ -128,6 +128,7 @@ class PEBinary : public PExpr {
virtual void dump(ostream&out) const;
virtual NetNet* elaborate_net(Design*des, const string&path) const;
virtual NetExpr*elaborate_expr(Design*des, const string&path) const;
private:
char op_;
@ -137,6 +138,13 @@ class PEBinary : public PExpr {
/*
* $Log: PExpr.h,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:54 steve
* Introduce verilog to CVS.
*

16
Statement.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: Statement.cc,v 1.1 1998/11/03 23:28:55 steve Exp $"
#ident "$Id: Statement.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include "Statement.h"
@ -57,9 +57,23 @@ PCallTask::PCallTask(const string&n, const list<PExpr*>&p)
}
PCondit::~PCondit()
{
delete expr_;
delete if_;
delete else_;
}
/*
* $Log: Statement.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:55 steve
* Introduce verilog to CVS.
*

29
Statement.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: Statement.h,v 1.1 1998/11/03 23:28:56 steve Exp $"
#ident "$Id: Statement.h,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include <string>
@ -146,6 +146,26 @@ class PCallTask : public Statement {
PExpr**const parms_;
};
class PCondit : public Statement {
public:
PCondit(PExpr*ex, Statement*i, Statement*e)
: expr_(ex), if_(i), else_(e) { }
~PCondit();
virtual NetProc* elaborate(Design*des, const string&path) const;
virtual void dump(ostream&out, unsigned ind) const;
private:
PExpr*expr_;
Statement*if_;
Statement*else_;
private: // not implemented
PCondit(const PCondit&);
PCondit& operator= (const PCondit&);
};
class PDelayStatement : public Statement {
public:
@ -186,6 +206,13 @@ class PNoop : public Statement {
/*
* $Log: Statement.h,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:56 steve
* Introduce verilog to CVS.
*

44
design_dump.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: design_dump.cc,v 1.1 1998/11/03 23:28:56 steve Exp $"
#ident "$Id: design_dump.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
/*
@ -202,6 +202,18 @@ void NetBlock::dump(ostream&o, unsigned ind) const
o << setw(ind) << "" << "end" << endl;
}
void NetCondit::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "if (";
expr_->dump(o);
o << ")" << endl;
if_->dump(o, ind+4);
if (else_) {
o << setw(ind) << "" << "else" << endl;
else_->dump(o, ind+4);
}
}
void NetPDelay::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "#" << delay_ << endl;
@ -261,6 +273,24 @@ void NetExpr::dump(ostream&o) const
o << "(?)";
}
void NetEBinary::dump(ostream&o) const
{
o << "(";
left_->dump(o);
o << ")";
switch (op_) {
default:
o << op_;
break;
case 'e':
o << "==";
break;
}
o << "(";
right_->dump(o);
o << ")";
}
void NetEConst::dump(ostream&o) const
{
if (value_.is_string())
@ -274,6 +304,11 @@ void NetEIdent::dump(ostream&o) const
o << name_;
}
void NetESignal::dump(ostream&o) const
{
o << sig_->name();
}
void NetEUnary::dump(ostream&o) const
{
o << op_ << "(";
@ -316,6 +351,13 @@ void Design::dump(ostream&o) const
/*
* $Log: design_dump.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:56 steve
* Introduce verilog to CVS.
*

37
elaborate.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: elaborate.cc,v 1.1 1998/11/03 23:28:56 steve Exp $"
#ident "$Id: elaborate.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
/*
@ -54,7 +54,7 @@ static void do_assign(Design*des, const string&path,
connect(lval->pin(idx), tmp->pin(idx));
delete tmp;
if (tmp = dynamic_cast<NetTmp*>(lval))
if ((tmp = dynamic_cast<NetTmp*>(lval)))
delete tmp;
} else if (NetTmp* tmp = dynamic_cast<NetTmp*>(lval)) {
@ -407,6 +407,12 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path) const
return sig;
}
NetExpr* PEBinary::elaborate_expr(Design*des, const string&path) const
{
return new NetEBinary(op_, left_->elaborate_expr(des, path),
right_->elaborate_expr(des, path));
}
NetExpr* PENumber::elaborate_expr(Design*des, const string&path) const
{
assert(value_);
@ -421,9 +427,13 @@ NetExpr* PEString::elaborate_expr(Design*des, const string&path) const
NetExpr*PEIdent::elaborate_expr(Design*des, const string&path) const
{
if (text_[0] == '$')
return new NetEIdent(text_);
else
return new NetEIdent(path+"."+text_);
return new NetEIdent(text_, 64);
else {
string name = path+"."+text_;
NetNet*net = des->find_signal(name);
assert(net);
return new NetESignal(net);
}
}
NetExpr* PExpr::elaborate_expr(Design*des, const string&path) const
@ -474,6 +484,16 @@ NetProc* PBlock::elaborate(Design*des, const string&path) const
return cur;
}
NetProc* PCondit::elaborate(Design*des, const string&path) const
{
NetExpr*expr = expr_->elaborate_expr(des, path);
NetProc*i = if_->elaborate(des, path);
NetProc*e = else_->elaborate(des, path);
NetCondit*res = new NetCondit(expr, i, e);
return res;
}
NetProc* PCallTask::elaborate(Design*des, const string&path) const
{
NetTask*cur = new NetTask(name(), nparms());
@ -598,6 +618,13 @@ Design* elaborate(const list<Module*>&modules, const string&root)
/*
* $Log: elaborate.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:56 steve
* Introduce verilog to CVS.
*

36
emit.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: emit.cc,v 1.1 1998/11/03 23:28:57 steve Exp $"
#ident "$Id: emit.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
/*
@ -79,6 +79,11 @@ void NetBlock::emit_proc(ostream&o, struct target_t*tgt) const
tgt->proc_block(o, this);
}
void NetCondit::emit_proc(ostream&o, struct target_t*tgt) const
{
tgt->proc_condit(o, this);
}
void NetPDelay::emit_proc(ostream&o, struct target_t*tgt) const
{
tgt->proc_delay(o, this);
@ -116,6 +121,18 @@ void NetBlock::emit_recurse(ostream&o, struct target_t*tgt) const
} while (cur != last_);
}
void NetCondit::emit_recurse_if(ostream&o, struct target_t*tgt) const
{
if (if_)
if_->emit_proc(o, tgt);
}
void NetCondit::emit_recurse_else(ostream&o, struct target_t*tgt) const
{
if (else_)
else_->emit_proc(o, tgt);
}
void Design::emit(ostream&o, struct target_t*tgt) const
{
tgt->start_design(o, this);
@ -147,6 +164,11 @@ void Design::emit(ostream&o, struct target_t*tgt) const
tgt->end_design(o, this);
}
void NetEBinary::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_binary(this);
}
void NetEConst::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_const(this);
@ -157,6 +179,11 @@ void NetEIdent::expr_scan(struct expr_scan_t*tgt) const
tgt->expr_ident(this);
}
void NetESignal::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_signal(this);
}
void NetEUnary::expr_scan(struct expr_scan_t*tgt) const
{
tgt->expr_unary(this);
@ -176,6 +203,13 @@ void emit(ostream&o, const Design*des, const char*type)
/*
* $Log: emit.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:57 steve
* Introduce verilog to CVS.
*

6
lexor.lex
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: lexor.lex,v 1.1 1998/11/03 23:28:59 steve Exp $"
#ident "$Id: lexor.lex,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
//# define YYSTYPE lexval
@ -63,6 +63,10 @@ static verinum*make_sized_hex(const char*txt);
"<=" { return K_LE; }
">=" { return K_GE; }
"==" { return K_EQ; }
"!=" { return K_NE; }
"===" { return K_CEQ; }
"!==" { return K_CNE; }
[;:\[\],()#=.@&!<|^~+-] { return yytext[0]; }

10
main.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: main.cc,v 1.1 1998/11/03 23:28:59 steve Exp $"
#ident "$Id: main.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include <stdio.h>
@ -88,7 +88,6 @@ int main(int argc, char*argv[])
int rc = pform_parse(input, modules);
if (rc) {
cerr << "I give up." << endl;
return rc;
}
@ -145,6 +144,13 @@ int main(int argc, char*argv[])
/*
* $Log: main.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:28:59 steve
* Introduce verilog to CVS.
*

27
netlist.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: netlist.cc,v 1.1 1998/11/03 23:29:00 steve Exp $"
#ident "$Id: netlist.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include <cassert>
@ -129,10 +129,28 @@ NetExpr::~NetExpr()
{
}
NetEBinary::~NetEBinary()
{
}
NetEConst::~NetEConst()
{
}
NetEBinary::NetEBinary(char op, NetExpr*l, NetExpr*r)
: op_(op), left_(l), right_(r)
{
switch (op_) {
case 'e':
natural_width(1);
break;
default:
natural_width(left_->natural_width() > right_->natural_width()
? left_->natural_width() : right_->natural_width());
break;
}
}
void Design::add_signal(NetNet*net)
{
assert(net->design_ == 0);
@ -235,6 +253,13 @@ void Design::add_process(NetProcTop*pro)
/*
* $Log: netlist.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:00 steve
* Introduce verilog to CVS.
*

91
netlist.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: netlist.h,v 1.1 1998/11/03 23:29:01 steve Exp $"
#ident "$Id: netlist.h,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
/*
@ -343,6 +343,27 @@ class NetBlock : public NetProc {
NetProc*last_;
};
/* A condit represents a conditional. It has an expression to test,
and a pair of statements to select from. */
class NetCondit : public NetProc {
public:
NetCondit(NetExpr*ex, NetProc*i, NetProc*e)
: expr_(ex), if_(i), else_(e) { }
NetExpr*expr() const { return expr_; }
void emit_recurse_if(ostream&, struct target_t*) const;
void emit_recurse_else(ostream&, struct target_t*) const;
virtual void emit_proc(ostream&, struct target_t*) const;
virtual void dump(ostream&, unsigned ind) const;
private:
NetExpr*expr_;
NetProc*if_;
NetProc*else_;
};
class NetPDelay : public NetProc {
public:
@ -457,21 +478,50 @@ class NetProcTop {
*/
class NetExpr {
public:
NetExpr() { }
explicit NetExpr(unsigned w =0) : width_(w) { }
virtual ~NetExpr() =0;
virtual void expr_scan(struct expr_scan_t*) const =0;
virtual void dump(ostream&) const;
unsigned natural_width() const { return width_; }
protected:
void natural_width(unsigned w) { width_ = w; }
private:
unsigned width_;
private: // not implemented
NetExpr(const NetExpr&);
NetExpr& operator=(const NetExpr&);
};
class NetEBinary : public NetExpr {
public:
NetEBinary(char op, NetExpr*l, NetExpr*r);
~NetEBinary();
const NetExpr*left() const { return left_; }
const NetExpr*right() const { return right_; }
char op() const { return op_; }
virtual void expr_scan(struct expr_scan_t*) const;
virtual void dump(ostream&) const;
private:
char op_;
NetExpr*left_;
NetExpr*right_;
};
class NetEConst : public NetExpr {
public:
NetEConst(const verinum&val) : value_(val) { }
NetEConst(const verinum&val)
: NetExpr(val.len()), value_(val) { }
~NetEConst();
const verinum&value() const { return value_; }
@ -487,7 +537,7 @@ class NetEUnary : public NetExpr {
public:
NetEUnary(char op, NetExpr*ex)
: op_(op), expr_(ex) { }
: NetExpr(ex->natural_width()), op_(op), expr_(ex) { }
char op() const { return op_; }
const NetExpr* expr() const { return expr_; }
@ -500,14 +550,12 @@ class NetEUnary : public NetExpr {
NetExpr*expr_;
};
/* XXXX Note: I do not know what to do about this. Elaboration should
expand vectors to scalers, but identifiers identify vectors, and
other issues. This class exists for now until I figure out the
right way to deal with identifiers. */
/* System identifiers are represented here. */
class NetEIdent : public NetExpr {
public:
NetEIdent(const string&n) : name_(n) { }
NetEIdent(const string&n, unsigned w)
: NetExpr(w), name_(n) { }
const string& name() const { return name_; }
@ -518,6 +566,24 @@ class NetEIdent : public NetExpr {
string name_;
};
/* When a signal shows up in an expression, this type represents
it. From this the expression can get any kind of access to the
structural signal. */
class NetESignal : public NetExpr {
public:
NetESignal(NetNet*n)
: NetExpr(n->pin_count()), sig_(n) { }
const string& name() const { return sig_->name(); }
virtual void expr_scan(struct expr_scan_t*) const;
virtual void dump(ostream&) const;
private:
NetNet*sig_;
};
/*
* This class contains an entire design. It includes processes and a
* netlist, and can be passed around from function to function.
@ -587,6 +653,13 @@ inline ostream& operator << (ostream&o, const NetExpr&exp)
/*
* $Log: netlist.h,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:01 steve
* Introduce verilog to CVS.
*

33
parse.y
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: parse.y,v 1.1 1998/11/03 23:29:01 steve Exp $"
#ident "$Id: parse.y,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include "parse_misc.h"
@ -53,7 +53,7 @@
%token <text> IDENTIFIER SYSTEM_IDENTIFIER STRING
%token <number> NUMBER
%token K_LE K_GE
%token K_LE K_GE K_EQ K_NE K_CEQ K_CNE
%token K_always K_and K_assign K_begin K_buf K_bufif0 K_bufif1 K_case
%token K_casex K_casez K_cmos K_deassign K_default K_defparam K_disable
%token K_edge K_else K_end K_endcase K_endfunction K_endmodule
@ -95,6 +95,7 @@
%left UNARY_PREC
%left '+' '-'
%left K_GE K_LE '<' '>'
%left K_EQ K_NE K_CEQ K_CNE
%left '&'
%left '^'
@ -179,6 +180,18 @@ expression
| expression '&' expression
{ $$ = new PEBinary('&', $1, $3);
}
| expression K_EQ expression
{ $$ = new PEBinary('e', $1, $3);
}
| expression K_CEQ expression
{ $$ = new PEBinary('E', $1, $3);
}
| expression K_NE expression
{ $$ = new PEBinary('n', $1, $3);
}
| expression K_CNE expression
{ $$ = new PEBinary('N', $1, $3);
}
;
@ -501,6 +514,22 @@ statement
{ $$ = pform_make_block(PBlock::BL_SEQ, 0); }
| K_fork K_join
{ $$ = pform_make_block(PBlock::BL_PAR, 0); }
| K_if '(' expression ')' statement_opt
{ PCondit*tmp = new PCondit($3, $5, 0);
$$ = tmp;
}
| K_if '(' expression ')' statement_opt K_else statement_opt
{ PCondit*tmp = new PCondit($3, $5, $7);
$$ = tmp;
}
| K_if '(' error ')' statement_opt
{ yyerror(@1, "Malformed conditional expression.");
$$ = $5;
}
| K_if '(' error ')' statement_opt K_else statement_opt
{ yyerror(@1, "Malformed conditional expression.");
$$ = $5;
}
| delay statement_opt
{ PDelayStatement*tmp = new PDelayStatement($1, $2);
$$ = tmp;

14
parse_misc.cc
View File

@ -17,21 +17,25 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: parse_misc.cc,v 1.1 1998/11/03 23:29:02 steve Exp $"
#ident "$Id: parse_misc.cc,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include "parse_misc.h"
# include <iostream.h>
extern const char*vl_file;
unsigned error_count = 0;
unsigned warn_count = 0;
void VLerror(const char*msg)
{
error_count += 1;
cerr << yylloc.text << ":" << yylloc.first_line << ": " << msg << endl;
}
void VLerror(const YYLTYPE&loc, const char*msg)
{
error_count += 1;
if (loc.text)
cerr << loc.text << ":";
@ -40,6 +44,7 @@ void VLerror(const YYLTYPE&loc, const char*msg)
void yywarn(const YYLTYPE&loc, const char*msg)
{
warn_count += 1;
if (loc.text)
cerr << loc.text << ":";
@ -53,6 +58,13 @@ int VLwrap()
/*
* $Log: parse_misc.cc,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:02 steve
* Introduce verilog to CVS.
*

10
parse_misc.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: parse_misc.h,v 1.1 1998/11/03 23:29:03 steve Exp $"
#ident "$Id: parse_misc.h,v 1.2 1998/11/07 17:05:05 steve Exp $"
#endif
# include <string>
@ -50,9 +50,17 @@ extern void VLerror(const YYLTYPE&loc, const char*msg);
#define yywarn VLwarn
extern void VLwarn(const YYLTYPE&loc, const char*msg);
extern unsigned error_count, warn_count;
/*
* $Log: parse_misc.h,v $
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:03 steve
* Introduce verilog to CVS.
*

16
pform.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: pform.cc,v 1.1 1998/11/03 23:29:03 steve Exp $"
#ident "$Id: pform.cc,v 1.2 1998/11/07 17:05:06 steve Exp $"
#endif
# include "pform.h"
@ -274,13 +274,25 @@ int pform_parse(FILE*input, list<Module*>&modules)
{
vl_input = input;
vl_modules = &modules;
error_count = 0;
warn_count = 0;
int rc = VLparse();
return rc;
if (rc) {
cerr << "I give up." << endl;
}
return error_count;
}
/*
* $Log: pform.cc,v $
* Revision 1.2 1998/11/07 17:05:06 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:03 steve
* Introduce verilog to CVS.
*

38
pform_dump.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: pform_dump.cc,v 1.1 1998/11/03 23:29:04 steve Exp $"
#ident "$Id: pform_dump.cc,v 1.2 1998/11/07 17:05:06 steve Exp $"
#endif
/*
@ -71,7 +71,25 @@ void PEUnary::dump(ostream&out) const
void PEBinary::dump(ostream&out) const
{
out << "(" << *left_ << ")" << op_ << "(" << *right_ << ")";
out << "(" << *left_ << ")";
switch (op_) {
case 'e':
out << "==";
break;
case 'E':
out << "===";
break;
case 'n':
out << "!=";
break;
case 'N':
out << "!==";
break;
default:
out << op_;
break;
}
out << "(" << *right_ << ")";
}
@ -210,6 +228,15 @@ void PCallTask::dump(ostream&out, unsigned ind) const
out << ";" << endl;
}
void PCondit::dump(ostream&out, unsigned ind) const
{
out << setw(ind) << "" << "if (" << *expr_ << ")" << endl;
if_->dump(out, ind+3);
if (else_) {
out << setw(ind) << "" << "else" << endl;
else_->dump(out, ind+3);
}
}
void PDelayStatement::dump(ostream&out, unsigned ind) const
{
@ -287,6 +314,13 @@ void pform_dump(ostream&out, Module*mod)
/*
* $Log: pform_dump.cc,v $
* Revision 1.2 1998/11/07 17:05:06 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:04 steve
* Introduce verilog to CVS.
*

80
t-vvm.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: t-vvm.cc,v 1.1 1998/11/03 23:29:05 steve Exp $"
#ident "$Id: t-vvm.cc,v 1.2 1998/11/07 17:05:06 steve Exp $"
#endif
# include <iostream>
@ -46,6 +46,7 @@ class target_vvm : public target_t {
virtual void start_process(ostream&os, const NetProcTop*);
virtual void proc_assign(ostream&os, const NetAssign*);
virtual void proc_block(ostream&os, const NetBlock*);
virtual void proc_condit(ostream&os, const NetCondit*);
virtual void proc_task(ostream&os, const NetTask*);
virtual void proc_event(ostream&os, const NetPEvent*);
virtual void proc_delay(ostream&os, const NetPDelay*);
@ -60,6 +61,11 @@ class target_vvm : public target_t {
unsigned thread_step_;
};
/*
* This class emits code for the rvalue of a procedural
* assignment. The expression is evaluated to fit the width
* specified.
*/
class vvm_proc_rval : public expr_scan_t {
public:
@ -75,7 +81,9 @@ class vvm_proc_rval : public expr_scan_t {
private:
virtual void expr_const(const NetEConst*);
virtual void expr_ident(const NetEIdent*);
virtual void expr_signal(const NetESignal*);
virtual void expr_unary(const NetEUnary*);
virtual void expr_binary(const NetEBinary*);
};
void vvm_proc_rval::expr_const(const NetEConst*expr)
@ -109,6 +117,11 @@ void vvm_proc_rval::expr_ident(const NetEIdent*expr)
result = mangle(expr->name());
}
void vvm_proc_rval::expr_signal(const NetESignal*expr)
{
result = mangle(expr->name());
}
void vvm_proc_rval::expr_unary(const NetEUnary*expr)
{
expr->expr()->expr_scan(this);
@ -130,6 +143,34 @@ void vvm_proc_rval::expr_unary(const NetEUnary*expr)
result = tname;
}
void vvm_proc_rval::expr_binary(const NetEBinary*expr)
{
if (width_ == 0) {
width_ = expr->left()->natural_width();
}
expr->left()->expr_scan(this);
string lres = result;
expr->right()->expr_scan(this);
string rres = result;
switch (expr->op()) {
case 'e':
result = string("vvm_binop_eq(") + lres + "," + rres + ")";
break;
case '+':
result = string("vvm_binop_plus(") + lres + "," + rres + ")";
break;
default:
cerr << "vvm: Unhandled binary op `" << expr->op() << "': "
<< *expr << endl;
os_ << lres << ";" << endl;
result = lres;
break;
}
}
static string emit_proc_rval(ostream&os, unsigned width, const NetExpr*expr)
{
vvm_proc_rval scan (os, width);
@ -148,6 +189,7 @@ class vvm_parm_rval : public expr_scan_t {
private:
virtual void expr_const(const NetEConst*);
virtual void expr_ident(const NetEIdent*);
virtual void expr_signal(const NetESignal*);
private:
ostream&os_;
@ -170,16 +212,21 @@ void vvm_parm_rval::expr_ident(const NetEIdent*expr)
"(vvm_calltf_parm::TIME);" << endl;
result = res;
} else {
string res = make_temp();
os_ << " vvm_calltf_parm::SIG " << res << ";" << endl;
os_ << " " << res << ".bits = &" <<
mangle(expr->name()) << ";" << endl;
os_ << " " << res << ".mon = &" <<
mangle(expr->name()) << "_mon;" << endl;
result = res;
cerr << "Unhandled identifier: " << expr->name() << endl;
}
}
void vvm_parm_rval::expr_signal(const NetESignal*expr)
{
string res = make_temp();
os_ << " vvm_calltf_parm::SIG " << res << ";" << endl;
os_ << " " << res << ".bits = &" <<
mangle(expr->name()) << ";" << endl;
os_ << " " << res << ".mon = &" <<
mangle(expr->name()) << "_mon;" << endl;
result = res;
}
static string emit_parm_rval(ostream&os, const NetExpr*expr)
{
vvm_parm_rval scan (os);
@ -401,6 +448,16 @@ void target_vvm::proc_block(ostream&os, const NetBlock*net)
net->emit_recurse(os, this);
}
void target_vvm::proc_condit(ostream&os, const NetCondit*net)
{
string expr = emit_proc_rval(os, 0, net->expr());
os << " if (" << expr << "[0] == V1) {" << endl;
net->emit_recurse_if(os, this);
os << " } else {" << endl;
net->emit_recurse_else(os, this);
os << " }" << endl;
}
void target_vvm::proc_task(ostream&os, const NetTask*net)
{
if (net->name()[0] == '$') {
@ -486,6 +543,13 @@ extern const struct target tgt_vvm = {
};
/*
* $Log: t-vvm.cc,v $
* Revision 1.2 1998/11/07 17:05:06 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:05 steve
* Introduce verilog to CVS.
*

28
target.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: target.cc,v 1.1 1998/11/03 23:29:06 steve Exp $"
#ident "$Id: target.cc,v 1.2 1998/11/07 17:05:06 steve Exp $"
#endif
# include "target.h"
@ -67,6 +67,13 @@ void target_t::proc_block(ostream&os, const NetBlock*)
{
}
void target_t::proc_condit(ostream&os, const NetCondit*condit)
{
cerr << "target (" << typeid(*this).name() << "): "
"Unhandled conditional:" << endl;
condit->dump(cerr, 6);
}
void target_t::proc_delay(ostream&os, const NetPDelay*)
{
cerr << "target (" << typeid(*this).name() << "): "
@ -107,14 +114,33 @@ void expr_scan_t::expr_ident(const NetEIdent*)
"unhandled expr_ident." << endl;
}
void expr_scan_t::expr_signal(const NetESignal*)
{
cerr << "expr_scan_t (" << typeid(*this).name() << "): "
"unhandled expr_signal." << endl;
}
void expr_scan_t::expr_unary(const NetEUnary*)
{
cerr << "expr_scan_t (" << typeid(*this).name() << "): "
"unhandled expr_unary." << endl;
}
void expr_scan_t::expr_binary(const NetEBinary*ex)
{
cerr << "expr_scan_t (" << typeid(*this).name() << "): "
"unhandled expr_binary: " <<*ex << endl;
}
/*
* $Log: target.cc,v $
* Revision 1.2 1998/11/07 17:05:06 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:06 steve
* Introduce verilog to CVS.
*

12
target.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: target.h,v 1.1 1998/11/03 23:29:06 steve Exp $"
#ident "$Id: target.h,v 1.2 1998/11/07 17:05:06 steve Exp $"
#endif
# include "netlist.h"
@ -70,6 +70,7 @@ struct target_t {
/* Various kinds of process nodes are dispatched through these. */
virtual void proc_assign(ostream&os, const NetAssign*);
virtual void proc_block(ostream&os, const NetBlock*);
virtual void proc_condit(ostream&os, const NetCondit*);
virtual void proc_task(ostream&os, const NetTask*);
virtual void proc_event(ostream&os, const NetPEvent*);
@ -88,7 +89,9 @@ struct expr_scan_t {
virtual ~expr_scan_t();
virtual void expr_const(const NetEConst*);
virtual void expr_ident(const NetEIdent*);
virtual void expr_signal(const NetESignal*);
virtual void expr_unary(const NetEUnary*);
virtual void expr_binary(const NetEBinary*);
};
@ -108,6 +111,13 @@ extern const struct target *target_table[];
/*
* $Log: target.h,v $
* Revision 1.2 1998/11/07 17:05:06 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:06 steve
* Introduce verilog to CVS.
*