Wrap up vecc4 support for left/right shift expressions.
This commit is contained in:
Stephen Williams
parent
6a93b6a7e4
commit
b0a9430e98
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@ -1294,152 +1294,6 @@ static struct vector_info draw_binary_expr_logic(ivl_expr_t expr,
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return lv;
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return lv;
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}
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}
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/*
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* Draw code to evaluate the << expression. Use the %shiftl/i0
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* or %shiftr/i0 instruction to do the real work of shifting. This
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* means that I can handle both left and right shifts in this
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* function, with the only difference the opcode I generate at the
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* end.
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*/
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static struct vector_info draw_binary_expr_lrs(ivl_expr_t expr, unsigned wid)
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{
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ivl_expr_t le = ivl_expr_oper1(expr);
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ivl_expr_t re = ivl_expr_oper2(expr);
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const char*opcode = "?";
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struct vector_info lv;
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/* Evaluate the expression that is to be shifted. */
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switch (ivl_expr_opcode(expr)) {
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case 'l': /* << (left shift) */
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lv = draw_eval_expr_wid(le, wid, 0);
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/* Shifting 0 gets 0, if we can be sure the shift value
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contains no 'x' or 'z' bits. */
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if ((lv.base == 0) && (ivl_expr_value(re) == IVL_VT_BOOL))
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return lv;
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if (lv.base < 4) {
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struct vector_info tmp;
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tmp.base = allocate_vector(lv.wid);
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tmp.wid = lv.wid;
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if (tmp.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of left shift (<<).\n",
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ivl_expr_file(expr), ivl_expr_lineno(expr),
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wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%mov %u, %u, %u;\n",
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tmp.base, lv.base, lv.wid);
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lv = tmp;
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}
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opcode = "%shiftl";
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break;
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case 'r': /* >> (unsigned right shift) */
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/* with the right shift, there may be high bits that are
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shifted into the desired width of the expression, so
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we let the expression size itself, if it is bigger
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then what is requested of us. */
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if (wid > ivl_expr_width(le)) {
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lv = draw_eval_expr_wid(le, wid, 0);
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} else {
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lv = draw_eval_expr_wid(le, ivl_expr_width(le), 0);
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}
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/* Shifting 0 gets 0, if we can be sure the shift value
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contains no 'x' or 'z' bits. */
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if ((lv.base == 0) && (ivl_expr_value(re) == IVL_VT_BOOL))
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return lv;
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if (lv.base < 4) {
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struct vector_info tmp;
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tmp.base = allocate_vector(lv.wid);
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tmp.wid = lv.wid;
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if (tmp.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of right shift (>>).\n",
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ivl_expr_file(expr), ivl_expr_lineno(expr),
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lv.wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%mov %u, %u, %u;\n",
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tmp.base, lv.base, lv.wid);
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lv = tmp;
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}
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opcode = "%shiftr";
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break;
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case 'R': /* >>> (signed right shift) */
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/* with the right shift, there may be high bits that are
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shifted into the desired width of the expression, so
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we let the expression size itself, if it is bigger
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then what is requested of us. */
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if (wid > ivl_expr_width(le)) {
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lv = draw_eval_expr_wid(le, wid, 0);
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} else {
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lv = draw_eval_expr_wid(le, ivl_expr_width(le), 0);
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}
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/* Shifting 0 gets 0, if we can be sure the shift value
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contains no 'x' or 'z' bits. */
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if ((lv.base == 0) && (ivl_expr_value(re) == IVL_VT_BOOL))
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return lv;
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/* Similarly, sign extending any constant bit begets itself,
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if this expression is signed. */
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if ((lv.base < 4) && ivl_expr_signed(expr)
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&& (ivl_expr_value(re) == IVL_VT_BOOL))
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return lv;
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if (lv.base < 4) {
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struct vector_info tmp;
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tmp.base = allocate_vector(lv.wid);
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tmp.wid = lv.wid;
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if (tmp.base == 0) {
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fprintf(stderr, "%s:%u: vvp.tgt error: "
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"Unable to allocate %u thread bits "
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"for result of right shift (>>>).\n",
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ivl_expr_file(expr), ivl_expr_lineno(expr),
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lv.wid);
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vvp_errors += 1;
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}
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fprintf(vvp_out, " %%mov %u, %u, %u;\n",
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tmp.base, lv.base, lv.wid);
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lv = tmp;
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}
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if (ivl_expr_signed(expr))
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opcode = "%shiftr/s";
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else
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opcode = "%shiftr";
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break;
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default:
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assert(0);
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}
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/* Figure out the shift amount and load that into the index
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register. The value may be a constant, or may need to be
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evaluated at run time. */
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eval_logic_into_integer(re,0);
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fprintf(vvp_out, " %s/i0 %u, %u;\n", opcode, lv.base, lv.wid);
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if (lv.base >= 8)
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save_expression_lookaside(lv.base, expr, lv.wid);
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return lv;
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}
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static struct vector_info draw_load_add_immediate(ivl_expr_t le,
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static struct vector_info draw_load_add_immediate(ivl_expr_t le,
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ivl_expr_t re,
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ivl_expr_t re,
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@ -1781,12 +1635,6 @@ static struct vector_info draw_binary_expr(ivl_expr_t expr,
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rv = draw_binary_expr_arith(expr, wid);
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rv = draw_binary_expr_arith(expr, wid);
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break;
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break;
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case 'l': /* << */
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case 'r': /* >> */
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case 'R': /* >>> */
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rv = draw_binary_expr_lrs(expr, wid);
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break;
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case 'o': /* || (logical or) */
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case 'o': /* || (logical or) */
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rv = draw_binary_expr_lor(expr, wid, stuff_ok_flag);
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rv = draw_binary_expr_lor(expr, wid, stuff_ok_flag);
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stuff_ok_used_flag = 1;
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stuff_ok_used_flag = 1;
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@ -1802,7 +1650,7 @@ static struct vector_info draw_binary_expr(ivl_expr_t expr,
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break;
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break;
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default:
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default:
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fprintf(stderr, "vvp.tgt error: unsupported binary (%c)\n",
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fprintf(stderr, "vvp.tgt error: draw_binary_expr: unsupported binary (%c)\n",
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ivl_expr_opcode(expr));
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ivl_expr_opcode(expr));
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assert(0);
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assert(0);
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}
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}
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@ -336,7 +336,10 @@ static void draw_binary_vec4_lrs(ivl_expr_t expr, int stuff_ok_flag)
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fprintf(vvp_out, " %%shiftr %u;\n", use_index_reg);
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fprintf(vvp_out, " %%shiftr %u;\n", use_index_reg);
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break;
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break;
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case 'R': /* >>> */
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case 'R': /* >>> */
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fprintf(vvp_out, " %%shiftrs %u;\n", use_index_reg);
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if (ivl_expr_signed(le))
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fprintf(vvp_out, " %%shiftr/s %u;\n", use_index_reg);
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else
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fprintf(vvp_out, " %%shiftr %u;\n", use_index_reg);
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break;
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break;
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default:
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default:
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assert(0);
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assert(0);
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@ -1168,29 +1168,6 @@ The index may be signed, and if less than 0, the beginning bits are
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not assigned. Also, if the bits go beyond the end of the signal, those
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not assigned. Also, if the bits go beyond the end of the signal, those
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bits are not written anywhere.
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bits are not written anywhere.
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* %shiftl/i0 <bit>, <wid> (XXXX Old implementation)
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This instruction shifts the vector left (towards more significant
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bits) by the amount in index register 0. The <bit> is the address of
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the LSB of the vector, and <wid> the width of the vector. The shift is
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done in place. Zero values are shifted in.
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For a negative shift the value is padded with 'bx.
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* %shiftr/i0 <bit>, <wid> (XXXX Old implementation)
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* %shiftr/s/i0 <bit>, <wid> (XXXX Old implementation)
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This instruction shifts the vector right (towards the less significant
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bits) by the amount in the index register 0. The <bit> is the address
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of the LSB of the vector, and <wid> is the width of the vector. The
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shift is done in place.
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%shiftr/i0 is an unsigned down shift, so zeros are shifted into the
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top bits. %shiftr/s/i0 is a signed shift, so the value is sign-extended.
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For a negative shift %shiftr/i0 will pad the value with 'bx.
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* %shiftl <idx>
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* %shiftl <idx>
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* %shiftr <idx>
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* %shiftr <idx>
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* %shiftr/s <idx>
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* %shiftr/s <idx>
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@ -1199,6 +1176,12 @@ These instructions shift the top value in the vec4 stack left (towards
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MSB) or right, possibly signed. The <idx> is the address of the index
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MSB) or right, possibly signed. The <idx> is the address of the index
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register that contains the amount to shift.
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register that contains the amount to shift.
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The instruction also checks flag bit 4. If it is true, the result is
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replaced with X instead of a shifted result. This is intended to
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detect that the index contents were not valid.
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For a negative shift, %shiftr will pad the vlaue with 'bx.
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* %split/vec4 <wid>
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* %split/vec4 <wid>
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Pull the top vec4 vector from the stack and split it into two
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Pull the top vec4 vector from the stack and split it into two
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182
vvp/vthread.cc
182
vvp/vthread.cc
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@ -5491,54 +5491,6 @@ bool of_SET_X0(vthread_t thr, vvp_code_t cp)
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return true;
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return true;
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}
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}
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#if 0
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bool of_SHIFTL_I0(vthread_t thr, vvp_code_t cp)
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{
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int base = cp->bit_idx[0];
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int wid = cp->number;
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int shift = thr->words[0].w_int;
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assert(base >= 4);
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thr_check_addr(thr, base+wid-1);
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if (thr_get_bit(thr, 4) == BIT4_1) {
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// The result is 'bx if the shift amount is undefined.
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vvp_vector4_t tmp (wid, BIT4_X);
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thr->bits4.set_vec(base, tmp);
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} else if (shift >= wid) {
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// Shift is so far that all value is shifted out. Write
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// in a constant 0 result.
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vvp_vector4_t tmp (wid, BIT4_0);
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thr->bits4.set_vec(base, tmp);
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} else if (shift > 0) {
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vvp_vector4_t tmp (thr->bits4, base, wid-shift);
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thr->bits4.set_vec(base+shift, tmp);
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// Fill zeros on the bottom
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vvp_vector4_t fil (shift, BIT4_0);
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thr->bits4.set_vec(base, fil);
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} else if (shift <= -wid) {
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vvp_vector4_t tmp (wid, BIT4_X);
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thr->bits4.set_vec(base, tmp);
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} else if (shift < 0) {
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// For a negative shift we pad with 'bx.
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int idx;
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for (idx = 0 ; (idx-shift) < wid ; idx += 1) {
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unsigned src = base + idx - shift;
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unsigned dst = base + idx;
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thr_put_bit(thr, dst, thr_get_bit(thr, src));
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}
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for ( ; idx < wid ; idx += 1)
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thr_put_bit(thr, base+idx, BIT4_X);
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}
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return true;
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}
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#endif
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/*
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/*
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* %shiftl <idx>
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* %shiftl <idx>
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*/
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*/
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@ -5581,61 +5533,6 @@ bool of_SHIFTL(vthread_t thr, vvp_code_t cp)
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return true;
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return true;
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}
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}
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#if 0
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/*
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* This is an unsigned right shift:
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*
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* %shiftr/i0 <bit>, <wid>
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*
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* The vector at address <bit> with width <wid> is shifted right a
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* number of bits stored in index/word register 0.
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*/
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bool of_SHIFTR_I0(vthread_t thr, vvp_code_t cp)
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{
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int base = cp->bit_idx[0];
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int wid = cp->number;
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int shift = thr->words[0].w_int;
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assert(base >= 4);
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thr_check_addr(thr, base+wid-1);
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if (thr_get_bit(thr, 4) == BIT4_1) {
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// The result is 'bx if the shift amount is undefined.
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vvp_vector4_t tmp (wid, BIT4_X);
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thr->bits4.set_vec(base, tmp);
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} else if (shift > wid) {
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// Shift so far that the entire vector is shifted out.
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vvp_vector4_t tmp (wid, BIT4_0);
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thr->bits4.set_vec(base, tmp);
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} else if (shift > 0) {
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// The mov method should handle overlapped source/dest
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thr->bits4.mov(base, base+shift, wid-shift);
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vvp_vector4_t tmp (shift, BIT4_0);
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thr->bits4.set_vec(base+wid-shift, tmp);
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} else if (shift < -wid) {
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// Negative shift is so far that all the value is shifted out.
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// Write in a constant 'bx result.
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vvp_vector4_t tmp (wid, BIT4_X);
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thr->bits4.set_vec(base, tmp);
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} else if (shift < 0) {
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// For a negative shift we pad with 'bx.
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vvp_vector4_t tmp (thr->bits4, base, wid+shift);
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thr->bits4.set_vec(base-shift, tmp);
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vvp_vector4_t fil (-shift, BIT4_X);
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thr->bits4.set_vec(base, fil);
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}
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return true;
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}
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#endif
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/*
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/*
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* %shiftr <idx>
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* %shiftr <idx>
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* This is an unsigned right shift. The <idx> is a number that selects
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* This is an unsigned right shift. The <idx> is a number that selects
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@ -5678,53 +5575,42 @@ bool of_SHIFTR(vthread_t thr, vvp_code_t cp)
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return true;
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return true;
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}
|
}
|
||||||
|
|
||||||
#if 0
|
/*
|
||||||
bool of_SHIFTR_S_I0(vthread_t thr, vvp_code_t cp)
|
* %shiftr/s <wid>
|
||||||
{
|
*/
|
||||||
int base = cp->bit_idx[0];
|
|
||||||
int wid = cp->number;
|
|
||||||
int shift = thr->words[0].w_int;
|
|
||||||
vvp_bit4_t sign = thr_get_bit(thr, base+wid-1);
|
|
||||||
|
|
||||||
if (thr_get_bit(thr, 4) == BIT4_1) {
|
|
||||||
// The result is 'bx if the shift amount is undefined.
|
|
||||||
vvp_vector4_t tmp (wid, BIT4_X);
|
|
||||||
thr->bits4.set_vec(base, tmp);
|
|
||||||
} else if (shift >= wid) {
|
|
||||||
for (int idx = 0 ; idx < wid ; idx += 1)
|
|
||||||
thr_put_bit(thr, base+idx, sign);
|
|
||||||
|
|
||||||
} else if (shift > 0) {
|
|
||||||
for (int idx = 0 ; idx < (wid-shift) ; idx += 1) {
|
|
||||||
unsigned src = base + idx + shift;
|
|
||||||
unsigned dst = base + idx;
|
|
||||||
thr_put_bit(thr, dst, thr_get_bit(thr, src));
|
|
||||||
}
|
|
||||||
for (int idx = (wid-shift) ; idx < wid ; idx += 1)
|
|
||||||
thr_put_bit(thr, base+idx, sign);
|
|
||||||
|
|
||||||
} else if (shift < -wid) {
|
|
||||||
// Negative shift is so far that all the value is
|
|
||||||
// shifted out. Write in a constant 'bx result.
|
|
||||||
vvp_vector4_t tmp (wid, BIT4_X);
|
|
||||||
thr->bits4.set_vec(base, tmp);
|
|
||||||
|
|
||||||
} else if (shift < 0) {
|
|
||||||
|
|
||||||
// For a negative shift we pad with 'bx.
|
|
||||||
vvp_vector4_t tmp (thr->bits4, base, wid+shift);
|
|
||||||
thr->bits4.set_vec(base-shift, tmp);
|
|
||||||
|
|
||||||
vvp_vector4_t fil (-shift, BIT4_X);
|
|
||||||
thr->bits4.set_vec(base, fil);
|
|
||||||
}
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
bool of_SHIFTR_S(vthread_t thr, vvp_code_t cp)
|
bool of_SHIFTR_S(vthread_t thr, vvp_code_t cp)
|
||||||
{
|
{
|
||||||
fprintf(stderr, "XXXX of_SHIFTR_S not implemented\n");
|
int use_index = cp->number;
|
||||||
|
int shift = thr->words[use_index].w_int;
|
||||||
|
|
||||||
|
vvp_vector4_t val = thr->pop_vec4();
|
||||||
|
int wid = val.size();
|
||||||
|
|
||||||
|
vvp_bit4_t sign_bit = val.value(val.size()-1);
|
||||||
|
|
||||||
|
if (thr->flags[4] == BIT4_1) {
|
||||||
|
val = vvp_vector4_t(wid, BIT4_X);
|
||||||
|
|
||||||
|
} else if (shift > wid) {
|
||||||
|
val = vvp_vector4_t(wid, sign_bit);
|
||||||
|
|
||||||
|
} else if (shift > 0) {
|
||||||
|
val.mov(0, shift, wid-shift);
|
||||||
|
|
||||||
|
vvp_vector4_t tmp (shift, sign_bit);
|
||||||
|
val.set_vec(wid-shift, tmp);
|
||||||
|
|
||||||
|
} else if (shift < -wid) {
|
||||||
|
val = vvp_vector4_t(wid, BIT4_X);
|
||||||
|
|
||||||
|
} else if (shift < 0) {
|
||||||
|
int use_shift = -shift;
|
||||||
|
val.mov(use_shift, 0, wid-use_shift);
|
||||||
|
vvp_vector4_t tmp(use_shift, BIT4_X);
|
||||||
|
val.set_vec(0, tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
thr->push_vec4(val);
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue