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Allow implicit wires in assign l-value.

This commit is contained in:
steve 2007-04-05 03:09:50 +00:00
parent dd995b3409
commit af913e7eb1
1 changed files with 13 additions and 3 deletions
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16
elaborate.cc
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ifdef HAVE_CVS_IDENT #ifdef HAVE_CVS_IDENT
#ident "$Id: elaborate.cc,v 1.366 2007/04/01 23:01:10 steve Exp $" #ident "$Id: elaborate.cc,v 1.367 2007/04/05 03:09:50 steve Exp $"
#endif #endif
# include "config.h" # include "config.h"
@ -87,10 +87,17 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
assert(pin(0)); assert(pin(0));
assert(pin(1)); assert(pin(1));
/* Normally, l-values to continuous assignments are NOT allowed
to implicitly declare nets. However, so many tools do allow
it that Icarus Verilog will allow it, at least if extensions
are enabled. */
bool implicit_lval_ok = false;
if (generation_flag == GN_VER2001X)
implicit_lval_ok = true;
/* Elaborate the l-value. */ /* Elaborate the l-value. */
NetNet*lval = pin(0)->elaborate_lnet(des, scope); NetNet*lval = pin(0)->elaborate_lnet(des, scope, implicit_lval_ok);
if (lval == 0) { if (lval == 0) {
des->errors += 1;
return; return;
} }
@ -3402,6 +3409,9 @@ Design* elaborate(list<perm_string>roots)
/* /*
* $Log: elaborate.cc,v $ * $Log: elaborate.cc,v $
* Revision 1.367 2007/04/05 03:09:50 steve
* Allow implicit wires in assign l-value.
*
* Revision 1.366 2007/04/01 23:01:10 steve * Revision 1.366 2007/04/01 23:01:10 steve
* Improve port mismatch error message. * Improve port mismatch error message.
* *