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Rename modules which are VHDL reserved words

This commit is contained in:
Nick Gasson 2010-08-09 23:01:29 +01:00 committed by Stephen Williams
parent 5e0f80afca
commit ae0fe9541d
1 changed files with 26 additions and 23 deletions
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49
tgt-vhdl/scope.cc
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@ -384,28 +384,6 @@ static void replace_consecutive_underscores(string& str)
} }
} }
// Return a valid VHDL name for a Verilog module
static string valid_entity_name(const string& module_name)
{
string name(module_name);
replace_consecutive_underscores(name);
if (name[0] == '_')
name = "Mod" + name;
if (*name.rbegin() == '_')
name += "Mod";
ostringstream ss;
int i = 1;
ss << name;
while (find_entity(ss.str())) {
// Keep adding an extra number until we get a unique name
ss.str("");
ss << name << i++;
}
return ss.str();
}
static bool is_vhdl_reserved_word(const string& word) static bool is_vhdl_reserved_word(const string& word)
{ {
// This is the complete list of VHDL reserved words // This is the complete list of VHDL reserved words
@ -434,6 +412,31 @@ static bool is_vhdl_reserved_word(const string& word)
return false; return false;
} }
// Return a valid VHDL name for a Verilog module
static string valid_entity_name(const string& module_name)
{
string name(module_name);
replace_consecutive_underscores(name);
if (name[0] == '_')
name = "module" + name;
if (*name.rbegin() == '_')
name += "module";
if (is_vhdl_reserved_word(name))
name += "_module";
ostringstream ss;
int i = 1;
ss << name;
while (find_entity(ss.str())) {
// Keep adding an extra number until we get a unique name
ss.str("");
ss << name << i++;
}
return ss.str();
}
// Make sure a signal name conforms to VHDL naming rules. // Make sure a signal name conforms to VHDL naming rules.
string make_safe_name(ivl_signal_t sig) string make_safe_name(ivl_signal_t sig)
{ {
@ -905,7 +908,7 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth)
// so we always create a pair and associate the architecture // so we always create a pair and associate the architecture
// with the entity for convenience (this also means that we // with the entity for convenience (this also means that we
// retain a 1-to-1 mapping of scope to VHDL element) // retain a 1-to-1 mapping of scope to VHDL element)
vhdl_arch *arch = new vhdl_arch(tname, "FromVerilog"); vhdl_arch *arch = new vhdl_arch(tname, "from_verilog");
vhdl_entity *ent = new vhdl_entity(tname, arch, depth); vhdl_entity *ent = new vhdl_entity(tname, arch, depth);
// Calculate the VHDL units to use for time values // Calculate the VHDL units to use for time values